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riscv-gcc-1
Commit 9d7877e3 by Richard Kenner
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(zero_extendqisi2... 

(zero_extendqisi2, zero_extendqihi2): Change anonymous patterns to use 16-bit
and 32-bit hexadecimal values and masks instead of bit ranges if constant.
(rotlsi3, lshrsi3, move condition codes, scc insns): Likewise.

From-SVN: r5231
parent 18192b41
Showing with 27 additions and 27 deletions
gcc/config/rs6000/rs6000.md
...@@ -70,7 +70,7 @@ ...@@ -70,7 +70,7 @@
"" ""
"@ "@
lbz%U1%X1 %0,%1 lbz%U1%X1 %0,%1
rlinm %0,%1,0,24,31" rlinm %0,%1,0,0x000000FF"
[(set_attr "type" "load,*")]) [(set_attr "type" "load,*")])
(define_insn "" (define_insn ""
...@@ -79,7 +79,7 @@ ...@@ -79,7 +79,7 @@
(const_int 0))) (const_int 0)))
(clobber (match_scratch:SI 2 "=r"))] (clobber (match_scratch:SI 2 "=r"))]
"" ""
"andil. %2,%1,255" "andil. %2,%1,0x00FF"
[(set_attr "type" "compare")]) [(set_attr "type" "compare")])
(define_insn "" (define_insn ""
...@@ -89,7 +89,7 @@ ...@@ -89,7 +89,7 @@
(set (match_operand:SI 0 "gpc_reg_operand" "=r") (set (match_operand:SI 0 "gpc_reg_operand" "=r")
(zero_extend:SI (match_dup 1)))] (zero_extend:SI (match_dup 1)))]
"" ""
"andil. %0,%1,255" "andil. %0,%1,0x00FF"
[(set_attr "type" "compare")]) [(set_attr "type" "compare")])
(define_expand "zero_extendqihi2" (define_expand "zero_extendqihi2"
...@@ -104,7 +104,7 @@ ...@@ -104,7 +104,7 @@
"" ""
"@ "@
lbz%U1%X1 %0,%1 lbz%U1%X1 %0,%1
rlinm %0,%1,0,24,31" rlinm %0,%1,0,0x000000FF"
[(set_attr "type" "load,*")]) [(set_attr "type" "load,*")])
(define_expand "zero_extendhisi2" (define_expand "zero_extendhisi2"
...@@ -119,7 +119,7 @@ ...@@ -119,7 +119,7 @@
"" ""
"@ "@
lhz%U1%X1 %0,%1 lhz%U1%X1 %0,%1
rlinm %0,%1,0,16,31" rlinm %0,%1,0,0x0000FFFF"
[(set_attr "type" "load,*")]) [(set_attr "type" "load,*")])
(define_insn "" (define_insn ""
...@@ -128,7 +128,7 @@ ...@@ -128,7 +128,7 @@
(const_int 0))) (const_int 0)))
(clobber (match_scratch:SI 2 "=r"))] (clobber (match_scratch:SI 2 "=r"))]
"" ""
"andil. %2,%1,65535" "andil. %2,%1,0xFFFF"
[(set_attr "type" "compare")]) [(set_attr "type" "compare")])
(define_insn "" (define_insn ""
...@@ -138,7 +138,7 @@ ...@@ -138,7 +138,7 @@
(set (match_operand:SI 0 "gpc_reg_operand" "=r") (set (match_operand:SI 0 "gpc_reg_operand" "=r")
(zero_extend:SI (match_dup 1)))] (zero_extend:SI (match_dup 1)))]
"" ""
"andil. %0,%1,65535" "andil. %0,%1,0xFFFF"
[(set_attr "type" "compare")]) [(set_attr "type" "compare")])
(define_expand "extendhisi2" (define_expand "extendhisi2"
...@@ -1165,7 +1165,7 @@ ...@@ -1165,7 +1165,7 @@
(rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r") (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r")
(match_operand:SI 2 "reg_or_cint_operand" "ri")))] (match_operand:SI 2 "reg_or_cint_operand" "ri")))]
"" ""
"rl%I2nm %0,%1,%h2,0,31") "rl%I2nm %0,%1,%h2,0xFFFFFFFF")
(define_insn "" (define_insn ""
[(set (match_operand:CC 0 "cc_reg_operand" "=x") [(set (match_operand:CC 0 "cc_reg_operand" "=x")
...@@ -1174,7 +1174,7 @@ ...@@ -1174,7 +1174,7 @@
(const_int 0))) (const_int 0)))
(clobber (match_scratch:SI 3 "=r"))] (clobber (match_scratch:SI 3 "=r"))]
"" ""
"rl%I2nm. %3,%1,%h2,0,31" "rl%I2nm. %3,%1,%h2,0xFFFFFFFF"
[(set_attr "type" "delayed_compare")]) [(set_attr "type" "delayed_compare")])
(define_insn "" (define_insn ""
...@@ -1185,7 +1185,7 @@ ...@@ -1185,7 +1185,7 @@
(set (match_operand:SI 0 "gpc_reg_operand" "=r") (set (match_operand:SI 0 "gpc_reg_operand" "=r")
(rotate:SI (match_dup 1) (match_dup 2)))] (rotate:SI (match_dup 1) (match_dup 2)))]
"" ""
"rl%I2nm. %0,%1,%h2,0,31" "rl%I2nm. %0,%1,%h2,0xFFFFFFFF"
[(set_attr "type" "delayed_compare")]) [(set_attr "type" "delayed_compare")])
(define_insn "" (define_insn ""
...@@ -1228,7 +1228,7 @@ ...@@ -1228,7 +1228,7 @@
(rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r") (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r")
(match_operand:SI 2 "reg_or_cint_operand" "ri")) 0)))] (match_operand:SI 2 "reg_or_cint_operand" "ri")) 0)))]
"" ""
"rl%I2nm %0,%1,%h2,24,31") "rl%I2nm %0,%1,%h2,0x000000FF")
(define_insn "" (define_insn ""
[(set (match_operand:CC 0 "cc_reg_operand" "=x") [(set (match_operand:CC 0 "cc_reg_operand" "=x")
...@@ -1239,7 +1239,7 @@ ...@@ -1239,7 +1239,7 @@
(const_int 0))) (const_int 0)))
(clobber (match_scratch:SI 3 "=r"))] (clobber (match_scratch:SI 3 "=r"))]
"" ""
"rl%I2nm. %3,%1,%h2,24,31" "rl%I2nm. %3,%1,%h2,0x000000FF"
[(set_attr "type" "delayed_compare")]) [(set_attr "type" "delayed_compare")])
(define_insn "" (define_insn ""
...@@ -1252,7 +1252,7 @@ ...@@ -1252,7 +1252,7 @@
(set (match_operand:SI 0 "gpc_reg_operand" "=r") (set (match_operand:SI 0 "gpc_reg_operand" "=r")
(zero_extend:SI (subreg:QI (rotate:SI (match_dup 1) (match_dup 2)) 0)))] (zero_extend:SI (subreg:QI (rotate:SI (match_dup 1) (match_dup 2)) 0)))]
"" ""
"rl%I2nm. %0,%1,%h2,24,31" "rl%I2nm. %0,%1,%h2,0x000000FF"
[(set_attr "type" "delayed_compare")]) [(set_attr "type" "delayed_compare")])
(define_insn "" (define_insn ""
...@@ -1262,7 +1262,7 @@ ...@@ -1262,7 +1262,7 @@
(rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r") (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r")
(match_operand:SI 2 "reg_or_cint_operand" "ri")) 0)))] (match_operand:SI 2 "reg_or_cint_operand" "ri")) 0)))]
"" ""
"rl%I2nm %0,%1,%h2,16,31") "rl%I2nm %0,%1,%h2,0x0000FFFF")
(define_insn "" (define_insn ""
[(set (match_operand:CC 0 "cc_reg_operand" "=x") [(set (match_operand:CC 0 "cc_reg_operand" "=x")
...@@ -1273,7 +1273,7 @@ ...@@ -1273,7 +1273,7 @@
(const_int 0))) (const_int 0)))
(clobber (match_scratch:SI 3 "=r"))] (clobber (match_scratch:SI 3 "=r"))]
"" ""
"rl%I2nm. %3,%1,%h2,16,31" "rl%I2nm. %3,%1,%h2,0x0000FFFF"
[(set_attr "type" "delayed_compare")]) [(set_attr "type" "delayed_compare")])
(define_insn "" (define_insn ""
...@@ -1286,7 +1286,7 @@ ...@@ -1286,7 +1286,7 @@
(set (match_operand:SI 0 "gpc_reg_operand" "=r") (set (match_operand:SI 0 "gpc_reg_operand" "=r")
(zero_extend:SI (subreg:HI (rotate:SI (match_dup 1) (match_dup 2)) 0)))] (zero_extend:SI (subreg:HI (rotate:SI (match_dup 1) (match_dup 2)) 0)))]
"" ""
"rl%I2nm. %0,%1,%h2,16,31" "rl%I2nm. %0,%1,%h2,0x0000FFFF"
[(set_attr "type" "delayed_compare")]) [(set_attr "type" "delayed_compare")])
;; Note that we use "sle." instead of "sl." so that we can set ;; Note that we use "sle." instead of "sl." so that we can set
...@@ -1442,7 +1442,7 @@ ...@@ -1442,7 +1442,7 @@
(lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r") (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
(match_operand:SI 2 "const_int_operand" "i")) 0)))] (match_operand:SI 2 "const_int_operand" "i")) 0)))]
"includes_rshift_p (operands[2], gen_rtx (CONST_INT, VOIDmode, 255))" "includes_rshift_p (operands[2], gen_rtx (CONST_INT, VOIDmode, 255))"
"rlinm %0,%1,%s2,24,31") "rlinm %0,%1,%s2,0x000000FF")
(define_insn "" (define_insn ""
[(set (match_operand:CC 0 "cc_reg_operand" "=x") [(set (match_operand:CC 0 "cc_reg_operand" "=x")
...@@ -1454,7 +1454,7 @@ ...@@ -1454,7 +1454,7 @@
(const_int 0))) (const_int 0)))
(clobber (match_scratch:SI 3 "=r"))] (clobber (match_scratch:SI 3 "=r"))]
"includes_rshift_p (operands[2], gen_rtx (CONST_INT, VOIDmode, 255))" "includes_rshift_p (operands[2], gen_rtx (CONST_INT, VOIDmode, 255))"
"rlinm. %3,%1,%s2,24,31" "rlinm. %3,%1,%s2,0x000000FF"
[(set_attr "type" "delayed_compare")]) [(set_attr "type" "delayed_compare")])
(define_insn "" (define_insn ""
...@@ -1468,7 +1468,7 @@ ...@@ -1468,7 +1468,7 @@
(set (match_operand:SI 0 "gpc_reg_operand" "=r") (set (match_operand:SI 0 "gpc_reg_operand" "=r")
(zero_extend:SI (subreg:QI (lshiftrt:SI (match_dup 1) (match_dup 2)) 0)))] (zero_extend:SI (subreg:QI (lshiftrt:SI (match_dup 1) (match_dup 2)) 0)))]
"includes_rshift_p (operands[2], gen_rtx (CONST_INT, VOIDmode, 255))" "includes_rshift_p (operands[2], gen_rtx (CONST_INT, VOIDmode, 255))"
"rlinm. %0,%1,%s2,24,31" "rlinm. %0,%1,%s2,0x000000FF"
[(set_attr "type" "delayed_compare")]) [(set_attr "type" "delayed_compare")])
(define_insn "" (define_insn ""
...@@ -1478,7 +1478,7 @@ ...@@ -1478,7 +1478,7 @@
(lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r") (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
(match_operand:SI 2 "const_int_operand" "i")) 0)))] (match_operand:SI 2 "const_int_operand" "i")) 0)))]
"includes_rshift_p (operands[2], gen_rtx (CONST_INT, VOIDmode, 65535))" "includes_rshift_p (operands[2], gen_rtx (CONST_INT, VOIDmode, 65535))"
"rlinm %0,%1,%s2,16,31") "rlinm %0,%1,%s2,0x0000FFFF")
(define_insn "" (define_insn ""
[(set (match_operand:CC 0 "cc_reg_operand" "=x") [(set (match_operand:CC 0 "cc_reg_operand" "=x")
...@@ -1490,7 +1490,7 @@ ...@@ -1490,7 +1490,7 @@
(const_int 0))) (const_int 0)))
(clobber (match_scratch:SI 3 "=r"))] (clobber (match_scratch:SI 3 "=r"))]
"includes_rshift_p (operands[2], gen_rtx (CONST_INT, VOIDmode, 65535))" "includes_rshift_p (operands[2], gen_rtx (CONST_INT, VOIDmode, 65535))"
"rlinm. %3,%1,%s2,16,31" "rlinm. %3,%1,%s2,0x0000FFFF"
[(set_attr "type" "delayed_compare")]) [(set_attr "type" "delayed_compare")])
(define_insn "" (define_insn ""
...@@ -1504,7 +1504,7 @@ ...@@ -1504,7 +1504,7 @@
(set (match_operand:SI 0 "gpc_reg_operand" "=r") (set (match_operand:SI 0 "gpc_reg_operand" "=r")
(zero_extend:SI (subreg:HI (lshiftrt:SI (match_dup 1) (match_dup 2)) 0)))] (zero_extend:SI (subreg:HI (lshiftrt:SI (match_dup 1) (match_dup 2)) 0)))]
"includes_rshift_p (operands[2], gen_rtx (CONST_INT, VOIDmode, 65535))" "includes_rshift_p (operands[2], gen_rtx (CONST_INT, VOIDmode, 65535))"
"rlinm. %0,%1,%s2,16,31" "rlinm. %0,%1,%s2,0x0000FFFF"
[(set_attr "type" "delayed_compare")]) [(set_attr "type" "delayed_compare")])
(define_insn "" (define_insn ""
...@@ -2250,9 +2250,9 @@ ...@@ -2250,9 +2250,9 @@
"@ "@
mcrf %0,%1 mcrf %0,%1
mtcrf 128,%1 mtcrf 128,%1
rlinm %1,%1,%F0,0,31\;mtcrf %R0,%1\;rlinm %1,%1,%f0,0,31 rlinm %1,%1,%F0,0xFFFFFFFF\;mtcrf %R0,%1\;rlinm %1,%1,%f0,0xFFFFFFFF
mfcr %0 mfcr %0
mfcr %0\;rlinm %0,%0,%f1,0,3 mfcr %0\;rlinm %0,%0,%f1,0xF0000000
ai %0,%1,0 ai %0,%1,0
l%U1%X1 %0,%1 l%U1%X1 %0,%1
st%U0%U1 %1,%0" st%U0%U1 %1,%0"
...@@ -3597,7 +3597,7 @@ ...@@ -3597,7 +3597,7 @@
[(match_operand 2 "cc_reg_operand" "y") [(match_operand 2 "cc_reg_operand" "y")
(const_int 0)]))] (const_int 0)]))]
"" ""
"%D1mfcr %0\;rlinm %0,%0,%J1,31,31" "%D1mfcr %0\;rlinm %0,%0,%J1,0x00000001"
[(set_attr "length" "12")]) [(set_attr "length" "12")])
(define_insn "" (define_insn ""
...@@ -3609,7 +3609,7 @@ ...@@ -3609,7 +3609,7 @@
(set (match_operand:SI 3 "gpc_reg_operand" "=r") (set (match_operand:SI 3 "gpc_reg_operand" "=r")
(match_op_dup 1 [(match_dup 2) (const_int 0)]))] (match_op_dup 1 [(match_dup 2) (const_int 0)]))]
"" ""
"%D1mfcr %3\;rlinm. %3,%3,%J1,31,31" "%D1mfcr %3\;rlinm. %3,%3,%J1,0x00000001"
[(set_attr "type" "delayed_compare") [(set_attr "type" "delayed_compare")
(set_attr "length" "12")]) (set_attr "length" "12")])
...@@ -3714,7 +3714,7 @@ ...@@ -3714,7 +3714,7 @@
[(match_operand 5 "cc_reg_operand" "y") [(match_operand 5 "cc_reg_operand" "y")
(const_int 0)]))] (const_int 0)]))]
"REGNO (operands[2]) != REGNO (operands[5])" "REGNO (operands[2]) != REGNO (operands[5])"
"%D1%D4mfcr %3\;rlinm %0,%3,%J1,31,31\;rlinm %3,%3,%J4,31,31" "%D1%D4mfcr %3\;rlinm %0,%3,%J1,0x00000001\;rlinm %3,%3,%J4,0x00000001"
[(set_attr "length" "20")]) [(set_attr "length" "20")])
;; There are some scc insns that can be done directly, without a compare. ;; There are some scc insns that can be done directly, without a compare.
......
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