[AArch64][SVE] Handle register-register pred_movs

pred_mov<mode> is defined for predicated loads and stores, where
exactly one of the operands is a register.  However, the instruction
condition only checked for "one" rather than "exactly one", and
Prathamesh found a case in which combine could fold a predicated
pattern to an all-register pred_mov<mode>.  The constraints would
then force one of the registers to memory.

This patch splits all-register forms into a normal move as soon
as possible, but also adds an all-register alternative in case the
instruction doesn't get split before RA (or in case the RA can use
inheritance to avoid a reload).

The testcase for this will be added to aarch64/sve-acle-branch.

2018-01-25  Richard Sandiford  <richard.sandiford@arm.com>

gcc/
	* config/aarch64/aarch64-sve.md (*pred_mov<mode>)
	(pred_mov<mode>): Handle all-register forms using both a new
	alternative and a split.

From-SVN: r268263

gcc/ChangeLog

+2019-01-25  Richard Sandiford  <richard.sandiford@arm.com>
+
+	* config/aarch64/aarch64-sve.md (*pred_mov<mode>)
+	(pred_mov<mode>): Handle all-register forms using both a new
+	alternative and a split.
+
 2019-01-25  Richard Biener  <rguenther@suse.de>
 
 	PR tree-optimization/86865

gcc/config/aarch64/aarch64-sve.md

@@ -170,18 +170,22 @@
 ;; all-true.  Note that this pattern is generated directly by
 ;; aarch64_emit_sve_pred_move, so changes to this pattern will
 ;; need changes there as well.
-(define_insn "*pred_mov<mode>"
-  [(set (match_operand:SVE_ALL 0 "nonimmediate_operand" "=w, m")
+(define_insn_and_split "*pred_mov<mode>"
+  [(set (match_operand:SVE_ALL 0 "nonimmediate_operand" "=w, w, m")
 	(unspec:SVE_ALL
-	  [(match_operand:<VPRED> 1 "register_operand" "Upl, Upl")
-	   (match_operand:SVE_ALL 2 "nonimmediate_operand" "m, w")]
+	  [(match_operand:<VPRED> 1 "register_operand" "Upl, Upl, Upl")
+	   (match_operand:SVE_ALL 2 "nonimmediate_operand" "w, m, w")]
 	  UNSPEC_MERGE_PTRUE))]
   "TARGET_SVE
    && (register_operand (operands[0], <MODE>mode)
        || register_operand (operands[2], <MODE>mode))"
   "@
+   #
    ld1<Vesize>\t%0.<Vetype>, %1/z, %2
    st1<Vesize>\t%2.<Vetype>, %1, %0"
+  "&& register_operand (operands[0], <MODE>mode)
+   && register_operand (operands[2], <MODE>mode)"
+  [(set (match_dup 0) (match_dup 2))]
 )
 
 (define_expand "movmisalign<mode>"
@@ -401,10 +405,10 @@
 ;; Predicated structure moves.  This works for both endiannesses but in
 ;; practice is only useful for big-endian.
 (define_insn_and_split "pred_mov<mode>"
-  [(set (match_operand:SVE_STRUCT 0 "aarch64_sve_struct_nonimmediate_operand" "=w, Utx")
+  [(set (match_operand:SVE_STRUCT 0 "aarch64_sve_struct_nonimmediate_operand" "=w, w, Utx")
 	(unspec:SVE_STRUCT
-	  [(match_operand:<VPRED> 1 "register_operand" "Upl, Upl")
-	   (match_operand:SVE_STRUCT 2 "aarch64_sve_struct_nonimmediate_operand" "Utx, w")]
+	  [(match_operand:<VPRED> 1 "register_operand" "Upl, Upl, Upl")
+	   (match_operand:SVE_STRUCT 2 "aarch64_sve_struct_nonimmediate_operand" "w, Utx, w")]
 	  UNSPEC_MERGE_PTRUE))]
   "TARGET_SVE
    && (register_operand (operands[0], <MODE>mode)