(extendsidi2,zero_extendsidi2): New patterns.

(adddi3,subdi3): Don't emit code for low part if known to be zero.

From-SVN: r3187

gcc/config/i386/i386.md

@@ -1025,17 +1025,36 @@
   return AS2 (movz%B0%L0,%1,%0);
 #endif
 }")
+
+(define_insn "zero_extendsidi2"
+  [(set (match_operand:DI 0 "register_operand" "=r")
+	(zero_extend:DI
+	 (match_operand:SI 1 "register_operand" "0")))]
+  ""
+  "*
+{
+  operands[0] = gen_rtx (REG, SImode, REGNO (operands[0]) + 1);
+  return AS2 (xor%L0,%0,%0);
+}")
 
 ;;- sign extension instructions
 
-/*
 (define_insn "extendsidi2"
-  [(set (match_operand:DI 0 "general_operand" "=a")
+  [(set (match_operand:DI 0 "register_operand" "=r")
 	(sign_extend:DI
-	 (match_operand:SI 1 "nonimmediate_operand" "a")))]
+	 (match_operand:SI 1 "register_operand" "0")))]
   ""
-  "clq")
-*/
+  "*
+{
+  if (REGNO (operands[0]) == 0)
+    return \"clq\";
+
+  operands[0] = gen_rtx (REG, SImode, REGNO (operands[0]));
+  output_asm_insn (AS2 (mov%L0,%0,%1), operands);
+
+  operands[0] = GEN_INT (31);
+  return AS2 (sar%L1,%0,%1);
+}")
 
 ;; Note that the i386 programmers' manual says that the opcodes
 ;; are named movsx..., but the assembler on Unix does not accept that.
@@ -1395,8 +1414,13 @@
 
   split_di (operands, 3, low, high);
 
-  output_asm_insn (AS2 (add%L0,%2,%0), low);
-  output_asm_insn (AS2 (adc%L0,%2,%0), high);
+  if (GET_CODE (low[2]) != CONST_INT || INTVAL (low[2]) != 0)
+    {
+      output_asm_insn (AS2 (add%L0,%2,%0), low);
+      output_asm_insn (AS2 (adc%L0,%2,%0), high);
+    }
+  else
+    output_asm_insn (AS2 (add%L0,%2,%0), high);
   RET;
 }")
 
@@ -1566,8 +1590,14 @@
 
   split_di (operands, 3, low, high);
 
-  output_asm_insn (AS2 (sub%L0,%2,%0), low);
-  output_asm_insn (AS2 (sbb%L0,%2,%0), high);
+  if (GET_CODE (low[2]) != CONST_INT || INTVAL (low[2]) != 0)
+    {
+      output_asm_insn (AS2 (sub%L0,%2,%0), low);
+      output_asm_insn (AS2 (sbb%L0,%2,%0), high);
+    }
+  else
+    output_asm_insn (AS2 (sub%L0,%2,%0), high);
+
   RET;
 }")