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Commit 9c0e94a5 by Richard Henderson Committed by Richard Henderson
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alpha.c (alpha_expand_prologue, [...]): New fns. 

        * alpha.c (alpha_expand_prologue, alpha_expand_epilogue): New fns.
        (output_prologue, output_epilogue): Merge VMS and OSF versions;
        Remove anything related to the actual code generation.
        (output_end_prologue): New function.
        (alpha_sa_mask, alpha_sa_size): Merge VMS and OSF versions.
        (alpha_does_function_need_gp): Return false for VMS.
        (alpha_function_needs_gp): Make static.
        (add_long_const): Delete.
        (summarize_insn): Don't assume a SUBREG is of a REG.
        Prototype all static functions.  Rename VMS-specific global
        variables vms_*.
        * alpha.h (TARGET_CAN_FAULT_IN_PROLOGUE): Default to 0.
        (FUNCTION_BOUNDARY): Align to cache line.
        (LOOP_ALIGN, ALIGN_LABEL_AFTER_BARRIER): Align to octaword.
        (FUNCTION_END_PROLOGUE): New macro.
        * alpha.md (attribute length): New.  Mark all insns.
        (return_internal, prologue_stack_probe_loop) New patterns.
        (prologue, init_fp, epilogue): New patterns.
        Disable peepholes.
        * linux.h (TARGET_CAN_FAULT_IN_PROLOGUE): Define.

From-SVN: r20528
parent ad1da1de
Showing with 162 additions and 50 deletions
gcc/ChangeLog
Tue Jun 16 16:49:26 1998 Richard Henderson <rth@cygnus.com>
* alpha.c (alpha_expand_prologue, alpha_expand_epilogue): New fns.
(output_prologue, output_epilogue): Merge VMS and OSF versions;
Remove anything related to the actual code generation.
(output_end_prologue): New function.
(alpha_sa_mask, alpha_sa_size): Merge VMS and OSF versions.
(alpha_does_function_need_gp): Return false for VMS.
(alpha_function_needs_gp): Make static.
(add_long_const): Delete.
(summarize_insn): Don't assume a SUBREG is of a REG.
Prototype all static functions. Rename VMS-specific global
variables vms_*.
* alpha.h (TARGET_CAN_FAULT_IN_PROLOGUE): Default to 0.
(FUNCTION_BOUNDARY): Align to cache line.
(LOOP_ALIGN, ALIGN_LABEL_AFTER_BARRIER): Align to octaword.
(FUNCTION_END_PROLOGUE): New macro.
* alpha.md (attribute length): New. Mark all insns.
(return_internal, prologue_stack_probe_loop) New patterns.
(prologue, init_fp, epilogue): New patterns.
Disable peepholes.
* linux.h (TARGET_CAN_FAULT_IN_PROLOGUE): Define.
Tue Jun 16 17:36:35 1998 Dave Brolley <brolley@cygnus.com>
* toplev.c (lang_options): Add -trigraphs option for cpplib.
......
gcc/config/alpha/alpha.h
......@@ -171,7 +171,9 @@ extern enum alpha_fp_trap_mode alpha_fptm;
#ifndef TARGET_AS_CAN_SUBTRACT_LABELS
#define TARGET_AS_CAN_SUBTRACT_LABELS TARGET_GAS
#endif
#ifndef TARGET_CAN_FAULT_IN_PROLOGUE
#define TARGET_CAN_FAULT_IN_PROLOGUE 0
#endif
/* Macro to define tables used to set the flags.
This is a list in braces of pairs in braces,
......@@ -371,7 +373,7 @@ extern void override_options ();
#define STACK_BOUNDARY 64
/* Allocation boundary (in *bits*) for the code of a function. */
#define FUNCTION_BOUNDARY 64
#define FUNCTION_BOUNDARY 256
/* Alignment of field after `int : 0' in a structure. */
#define EMPTY_FIELD_BOUNDARY 64
......@@ -387,20 +389,16 @@ extern void override_options ();
??? Kludge this and the next macro for the moment by not doing anything if
we don't optimize and also if we are writing ECOFF symbols to work around
a bug in DEC's assembler. */
/* Aligning past 2**3 wastes insn cache lines, and doesn't buy much
issue-wise on average anyway. */
#define LOOP_ALIGN(LABEL) \
(optimize > 0 && write_symbols != SDB_DEBUG ? 3 : 0)
(optimize > 0 && write_symbols != SDB_DEBUG ? 4 : 0)
/* This is how to align an instruction for optimal branching.
On Alpha we'll get better performance by aligning on a quadword
/* This is how to align an instruction for optimal branching. On
Alpha we'll get better performance by aligning on an octaword
boundary. */
/* Aligning past 2**3 wastes insn cache lines, and doesn't buy much
issue-wise on average anyway. */
#define ALIGN_LABEL_AFTER_BARRIER(FILE) \
(optimize > 0 && write_symbols != SDB_DEBUG ? 3 : 0)
(optimize > 0 && write_symbols != SDB_DEBUG ? 4 : 0)
/* No data type wants to be aligned rounder than this. */
#define BIGGEST_ALIGNMENT 64
......@@ -1118,7 +1116,11 @@ extern char *alpha_function_name;
is ever used in the function. This macro is responsible for
knowing which registers should not be saved even if used. */
#define FUNCTION_PROLOGUE(FILE, SIZE) output_prolog (FILE, SIZE)
#define FUNCTION_PROLOGUE(FILE, SIZE) output_prologue (FILE, SIZE)
/* This macro notes the end of the prologue. */
#define FUNCTION_END_PROLOGUE(FILE) output_end_prologue (FILE)
/* Output assembler code to FILE to increment profiler label # LABELNO
for profiling a function entry. Under OSF/1, profiling is enabled
......@@ -1179,7 +1181,7 @@ extern char *alpha_function_name;
of alloca; we also take advantage of it to omit stack adjustments
before returning. */
#define FUNCTION_EPILOGUE(FILE, SIZE) output_epilog (FILE, SIZE)
#define FUNCTION_EPILOGUE(FILE, SIZE) output_epilogue (FILE, SIZE)
/* Output assembler code for a block containing the constant parts
......@@ -1253,7 +1255,6 @@ extern char *alpha_function_name;
/* Attempt to turn on access permissions for the stack. */
#define TRANSFER_FROM_TRAMPOLINE \
\
void \
__enable_execute_stack (addr) \
void *addr; \
......
gcc/config/alpha/alpha.md
......@@ -37,7 +37,7 @@
;; 2 builtin_setjmp_receiver
;; 3 builtin_longjmp
;; 4 trapb
;; 5 prologue_stack_probe_loop
;; Processor type -- this attribute must exactly match the processor_type
;; enumeration in alpha.h.
......@@ -54,13 +54,20 @@
"ild,fld,ldsym,ist,fst,ibr,fbr,jsr,iadd,ilog,shift,icmov,fcmov,icmp,imul,fadd,fmul,fcpys,fdiv,fsqrt,misc,mvi,ftoi,itof"
(const_string "iadd"))
;; Define the operand size an insn operates on. Used primarily by mul
;; and div operations that have size dependant timings.
(define_attr "opsize" "si,di,udi" (const_string "di"))
;; The TRAP_TYPE attribute marks instructions that may generate traps
;; (which are imprecise and may need a trapb if software completion
;; is desired).
(define_attr "trap" "no,yes" (const_string "no"))
;; The length of an instruction sequence in bytes.
(define_attr "length" "" (const_int 4))
;; On EV4 there are two classes of resources to consider: resources needed
;; to issue, and resources needed to execute. IBUS[01] are in the first
......@@ -385,7 +392,8 @@
addl %1,$31,%0
ldl %0,%1
lds %0,%1\;cvtlq %0,%0"
[(set_attr "type" "iadd,ild,fld")])
[(set_attr "type" "iadd,ild,fld")
(set_attr "length" "*,*,8")])
;; Due to issues with CLASS_CANNOT_CHANGE_SIZE, we cannot use a subreg here.
(define_split
......@@ -917,6 +925,8 @@
"!TARGET_OPEN_VMS"
"")
;; Lengths of 8 for ldq $t12,__divq($gp); jsr $t9,($t12),__divq as
;; expanded by the assembler.
(define_insn ""
[(set (reg:DI 27)
(sign_extend:DI (match_operator:SI 1 "divmod_operator"
......@@ -925,7 +935,8 @@
(clobber (reg:DI 28))]
"!TARGET_OPEN_VMS"
"%E1 $24,$25,$27"
[(set_attr "type" "jsr")])
[(set_attr "type" "jsr")
(set_attr "length" "8")])
(define_insn ""
[(set (reg:DI 27)
......@@ -935,7 +946,8 @@
(clobber (reg:DI 28))]
"!TARGET_OPEN_VMS"
"%E1 $24,$25,$27"
[(set_attr "type" "jsr")])
[(set_attr "type" "jsr")
(set_attr "length" "8")])
;; Next are the basic logical operations. These only exist in DImode.
......@@ -2357,7 +2369,8 @@
(clobber (match_scratch:DI 4 "=&r"))]
""
"addq %0,%1,%4\;cmov%C2 %r3,%4,%0"
[(set_attr "type" "icmov")])
[(set_attr "type" "icmov")
(set_attr "length" "8")])
(define_split
[(set (match_operand:DI 0 "register_operand" "")
......@@ -3679,7 +3692,8 @@
jsr $26,($27),0\;ldgp $29,0($26)
bsr $26,$%0..ng
jsr $26,%0\;ldgp $29,0($26)"
[(set_attr "type" "jsr")])
[(set_attr "type" "jsr")
(set_attr "length" "12,*,12")])
(define_insn ""
[(call (mem:DI (match_operand:DI 0 "call_operand" "r,R,i"))
......@@ -3690,7 +3704,8 @@
jsr $26,(%0)
bsr $26,%0
jsr $26,%0"
[(set_attr "type" "jsr")])
[(set_attr "type" "jsr")
(set_attr "length" "*,*,12")])
(define_insn ""
[(call (mem:DI (match_operand:DI 0 "call_operand" "r,i"))
......@@ -3703,7 +3718,8 @@
"@
bis %2,%2,$27\;jsr $26,0\;ldq $27,0($29)
ldq $27,%2\;jsr $26,%0\;ldq $27,0($29)"
[(set_attr "type" "jsr")])
[(set_attr "type" "jsr")
(set_attr "length" "12,16")])
(define_insn ""
[(set (match_operand 0 "register_operand" "=rf,rf,rf")
......@@ -3716,7 +3732,8 @@
jsr $26,($27),0\;ldgp $29,0($26)
bsr $26,$%1..ng
jsr $26,%1\;ldgp $29,0($26)"
[(set_attr "type" "jsr")])
[(set_attr "type" "jsr")
(set_attr "length" "12,*,12")])
(define_insn ""
[(set (match_operand 0 "register_operand" "=rf,rf,rf")
......@@ -3728,7 +3745,8 @@
jsr $26,(%1)
bsr $26,%1
jsr $26,%1"
[(set_attr "type" "jsr")])
[(set_attr "type" "jsr")
(set_attr "length" "*,*,12")])
(define_insn ""
[(set (match_operand 0 "register_operand" "")
......@@ -3742,7 +3760,8 @@
"@
bis %3,%3,$27\;jsr $26,0\;ldq $27,0($29)
ldq $27,%3\;jsr $26,%1\;ldq $27,0($29)"
[(set_attr "type" "jsr")])
[(set_attr "type" "jsr")
(set_attr "length" "12,16")])
;; Call subroutine returning any type.
......@@ -3779,7 +3798,8 @@
(define_insn "blockage"
[(unspec_volatile [(const_int 0)] 1)]
""
"")
""
[(set_attr "length" "0")])
(define_insn "jump"
[(set (pc)
......@@ -3794,6 +3814,15 @@
"ret $31,($26),1"
[(set_attr "type" "ibr")])
;; Use a different pattern for functions which have non-trivial
;; epilogues so as not to confuse jump and reorg.
(define_insn "return_internal"
[(use (reg:DI 26))
(return)]
""
"ret $31,($26),1"
[(set_attr "type" "ibr")])
(define_insn "indirect_jump"
[(set (pc) (match_operand:DI 0 "register_operand" "r"))]
""
......@@ -3803,7 +3832,7 @@
(define_insn "nop"
[(const_int 0)]
""
"bis $31,$31,$31"
"nop"
[(set_attr "type" "ilog")])
(define_expand "tablejump"
......@@ -3900,7 +3929,8 @@
else
return \"addq %0,$29,%2\;jmp $31,(%2),0\";
}"
[(set_attr "type" "ibr")])
[(set_attr "type" "ibr")
(set_attr "length" "8")])
(define_insn ""
[(set (pc)
......@@ -5058,6 +5088,57 @@
}
}")
;; This is used by alpha_expand_prolog to do the same thing as above,
;; except we cannot at that time generate new basic blocks, so we hide
;; the loop in this one insn.
(define_insn "prologue_stack_probe_loop"
[(unspec_volatile [(match_operand 0 "register_operand" "r")
(match_operand 1 "register_operand" "r")] 5)]
""
"*
{
static int label_no;
int count_regno = REGNO (operands[0]);
int ptr_regno = REGNO (operands[1]);
char label[64];
/* Ho hum, output the hard way to get the label at the beginning of
the line. Wish there were a magic char you could get
asm_output_printf to do that. Then we could use %= as well and
get rid of the label_no bits here too. */
ASM_GENERATE_INTERNAL_LABEL (label, \"LSC\", label_no);
ASM_OUTPUT_INTERNAL_LABEL (asm_out_file, \"LSC\", label_no++);
fprintf (asm_out_file, \"\\tstq $31,-8192($%d)\\n\", ptr_regno);
fprintf (asm_out_file, \"\\tsubq $%d,1,$%d\\n\", count_regno, count_regno);
fprintf (asm_out_file, \"\\tlda $%d,-8192($%d)\\n\", ptr_regno, ptr_regno);
fprintf (asm_out_file, \"\\tbne $%d,\", count_regno);
assemble_name (asm_out_file, label);
putc ('\\n', asm_out_file);
return \"\";
}"
[(set_attr "length" "16")])
(define_expand "prologue"
[(clobber (const_int 0))]
""
"alpha_expand_prologue (); DONE;")
(define_insn "init_fp"
[(set (match_operand:DI 0 "register_operand" "r")
(match_operand:DI 1 "register_operand" "r"))
(clobber (mem:BLK (match_operand:DI 2 "register_operand" "r")))]
""
"bis %1,%1,%0")
(define_expand "epilogue"
[(clobber (const_int 0))]
""
"alpha_expand_epilogue (); DONE;")
(define_expand "builtin_longjmp"
[(unspec_volatile [(match_operand 0 "register_operand" "r")] 3)]
"! TARGET_OPEN_VMS && ! TARGET_WINDOWS_NT"
......@@ -5085,12 +5166,14 @@
(define_insn "builtin_setjmp_receiver"
[(unspec_volatile [(match_operand 0 "" "")] 2)]
"! TARGET_OPEN_VMS && ! TARGET_WINDOWS_NT && TARGET_AS_CAN_SUBTRACT_LABELS"
"\\n$LSJ%=:\;ldgp $29,$LSJ%=-%l0($27)")
"\\n$LSJ%=:\;ldgp $29,$LSJ%=-%l0($27)"
[(set_attr "length" "8")])
(define_insn ""
[(unspec_volatile [(match_operand 0 "" "")] 2)]
"! TARGET_OPEN_VMS && ! TARGET_WINDOWS_NT"
"br $27,$LSJ%=\\n$LSJ%=:\;ldgp $29,0($27)")
"br $27,$LSJ%=\\n$LSJ%=:\;ldgp $29,0($27)"
[(set_attr "length" "12")])
(define_expand "nonlocal_goto_receiver"
[(unspec_volatile [(const_int 0)] 1)
......@@ -5121,7 +5204,8 @@
(clobber (reg:DI 25))
(clobber (reg:DI 0))]
"TARGET_OPEN_VMS"
"lda $0,OTS$HOME_ARGS\;ldq $0,8($0)\;jsr $0,OTS$HOME_ARGS")
"lda $0,OTS$HOME_ARGS\;ldq $0,8($0)\;jsr $0,OTS$HOME_ARGS"
[(set_attr "length" "16")])
;; Close the trap shadow of preceeding instructions. This is generated
;; by alpha_reorg.
......@@ -5137,22 +5221,22 @@
;; Optimize sign-extension of SImode loads. This shows up in the wake of
;; reload when converting fp->int.
;;
;; ??? What to do when we are actually caring about the packing and
;; ??? What to do now that we actually care about the packing and
;; alignment of instructions? Perhaps reload can be enlightened, or
;; the peephole pass moved up after reload but before sched2.
(define_peephole
[(set (match_operand:SI 0 "register_operand" "=r")
(match_operand:SI 1 "memory_operand" "m"))
(set (match_operand:DI 2 "register_operand" "=r")
(sign_extend:DI (match_dup 0)))]
"dead_or_set_p (insn, operands[0])"
"ldl %2,%1")
(define_peephole
[(set (match_operand:SI 0 "register_operand" "=r")
(match_operand:SI 1 "hard_fp_register_operand" "f"))
(set (match_operand:DI 2 "register_operand" "=r")
(sign_extend:DI (match_dup 0)))]
"TARGET_CIX && dead_or_set_p (insn, operands[0])"
"ftois %1,%2")
;; the peephole pass moved up after reload but before sched2?
;
;(define_peephole
; [(set (match_operand:SI 0 "register_operand" "=r")
; (match_operand:SI 1 "memory_operand" "m"))
; (set (match_operand:DI 2 "register_operand" "=r")
; (sign_extend:DI (match_dup 0)))]
; "dead_or_set_p (insn, operands[0])"
; "ldl %2,%1")
;
;(define_peephole
; [(set (match_operand:SI 0 "register_operand" "=r")
; (match_operand:SI 1 "hard_fp_register_operand" "f"))
; (set (match_operand:DI 2 "register_operand" "=r")
; (sign_extend:DI (match_dup 0)))]
; "TARGET_CIX && dead_or_set_p (insn, operands[0])"
; "ftois %1,%2")
gcc/config/alpha/linux.h
......@@ -31,14 +31,18 @@ the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA. */
#define LIB_SPEC "%{pg:-lgmon} %{pg:-lc_p} %{!pg:-lc}"
/* Generate calls to memcpy, etc., not bcopy, etc. */
#define TARGET_MEM_FUNCTIONS
#define TARGET_MEM_FUNCTIONS 1
#undef FUNCTION_PROFILER
#define FUNCTION_PROFILER(FILE, LABELNO) \
fputs ("\tlda $28,_mcount\n\tjsr $28,($28),_mcount\n", (FILE))
/* Show that we need a GP when profiling. */
#define TARGET_PROFILING_NEEDS_GP
#define TARGET_PROFILING_NEEDS_GP 1
/* Don't care about faults in the prologue. */
#undef TARGET_CAN_FAULT_IN_PROLOGUE
#define TARGET_CAN_FAULT_IN_PROLOGUE 1
/* Emit RTL insns to initialize the variable parts of a trampoline.
FNADDR is an RTX for the address of the function's pure code.
......
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