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riscv-gcc-1
Commit 9b73c90a by Eric Botcazou Committed by Eric Botcazou
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re PR rtl-optimization/9888 (-mcpu=k6 -Os produces out of range loop instructions) 

	PR optimization/9888
	* config/i386/i386.md (movsi_1): Remove special alternatives
	for %eax register.
	(movsi_1_nointernunit): Likewise.
	(movhi_1): Likewise.
	* config/i386/i386.c (memory_address_length): Do not use
	short displacement when there is no base.
	(ix86_attr_length_address_default): Handle LEA instructions.

From-SVN: r64225
parent 57f989ce
Showing with 51 additions and 32 deletions
gcc/ChangeLog
2003-03-12 Eric Botcazou <ebotcazou@libertysurf.fr>
PR optimization/9888
* config/i386/i386.md (movsi_1): Remove special alternatives
for %eax register.
(movsi_1_nointernunit): Likewise.
(movhi_1): Likewise.
* config/i386/i386.c (memory_address_length): Do not use
short displacement when there is no base.
(ix86_attr_length_address_default): Handle LEA instructions.
2003-03-12 Neil Booth <neil@daikokuya.co.uk>
* c-cppbuiltin.c (builtin_define_std): Make non-static.
......
gcc/config/i386/i386.c
......@@ -11857,7 +11857,8 @@ memory_address_length (addr)
if (disp)
{
if (GET_CODE (disp) == CONST_INT
&& CONST_OK_FOR_LETTER_P (INTVAL (disp), 'K'))
&& CONST_OK_FOR_LETTER_P (INTVAL (disp), 'K')
&& base)
len = 1;
else
len = 4;
......@@ -11920,6 +11921,26 @@ ix86_attr_length_address_default (insn)
rtx insn;
{
int i;
if (get_attr_type (insn) == TYPE_LEA)
{
rtx set = PATTERN (insn);
if (GET_CODE (set) == SET)
;
else if (GET_CODE (set) == PARALLEL
&& GET_CODE (XVECEXP (set, 0, 0)) == SET)
set = XVECEXP (set, 0, 0);
else
{
#ifdef ENABLE_CHECKING
abort ();
#endif
return 0;
}
return memory_address_length (SET_SRC (set));
}
extract_insn_cached (insn);
for (i = recog_data.n_operands - 1; i >= 0; --i)
if (GET_CODE (recog_data.operand[i]) == MEM)
......
gcc/config/i386/i386.md
......@@ -1161,14 +1161,9 @@
(set_attr "mode" "SI")
(set_attr "length_immediate" "1")])
; The first alternative is used only to compute proper length of instruction.
; Reload's algorithm does not take into account the cost of spill instructions
; needed to free register in given class, so avoid it from choosing the first
; alternative when eax is not available.
(define_insn "*movsi_1"
[(set (match_operand:SI 0 "nonimmediate_operand" "=*?a,r,*?a,m,!*y,!rm,!*y,!*Y,!rm,!*Y")
(match_operand:SI 1 "general_operand" "im,rinm,rinm,rin,*y,*y,rm,*Y,*Y,rm"))]
[(set (match_operand:SI 0 "nonimmediate_operand" "=r,m,!*y,!rm,!*y,!*Y,!rm,!*Y")
(match_operand:SI 1 "general_operand" "rinm,rin,*y,*y,rm,*Y,*Y,rm"))]
"(TARGET_INTER_UNIT_MOVES || optimize_size)
&& (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)"
{
......@@ -1194,21 +1189,20 @@
}
}
[(set (attr "type")
(cond [(eq_attr "alternative" "4,5,6")
(cond [(eq_attr "alternative" "2,3,4")
(const_string "mmxmov")
(eq_attr "alternative" "7,8,9")
(eq_attr "alternative" "5,6,7")
(const_string "ssemov")
(and (ne (symbol_ref "flag_pic") (const_int 0))
(match_operand:SI 1 "symbolic_operand" ""))
(const_string "lea")
]
(const_string "imov")))
(set_attr "modrm" "0,*,0,*,*,*,*,*,*,*")
(set_attr "mode" "SI,SI,SI,SI,DI,SI,SI,TI,SI,SI")])
(set_attr "mode" "SI,SI,DI,SI,SI,TI,SI,SI")])
(define_insn "*movsi_1_nointernunit"
[(set (match_operand:SI 0 "nonimmediate_operand" "=*?a,r,*?a,m,!*y,!m,!*y,!*Y,!m,!*Y")
(match_operand:SI 1 "general_operand" "im,rinm,rinm,rin,*y,*y,m,*Y,*Y,m"))]
[(set (match_operand:SI 0 "nonimmediate_operand" "=r,m,!*y,!m,!*y,!*Y,!m,!*Y")
(match_operand:SI 1 "general_operand" "rinm,rin,*y,*y,m,*Y,*Y,m"))]
"(!TARGET_INTER_UNIT_MOVES && !optimize_size)
&& (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)"
{
......@@ -1234,17 +1228,16 @@
}
}
[(set (attr "type")
(cond [(eq_attr "alternative" "4,5,6")
(cond [(eq_attr "alternative" "2,3,4")
(const_string "mmxmov")
(eq_attr "alternative" "7,8,9")
(eq_attr "alternative" "5,6,7")
(const_string "ssemov")
(and (ne (symbol_ref "flag_pic") (const_int 0))
(match_operand:SI 1 "symbolic_operand" ""))
(const_string "lea")
]
(const_string "imov")))
(set_attr "modrm" "0,*,0,*,*,*,*,*,*,*")
(set_attr "mode" "SI,SI,SI,SI,DI,SI,SI,TI,SI,SI")])
(set_attr "mode" "SI,SI,DI,SI,SI,TI,SI,SI")])
;; Stores and loads of ax to arbitrary constant address.
;; We fake an second form of instruction to force reload to load address
......@@ -1317,14 +1310,9 @@
[(set_attr "type" "push")
(set_attr "mode" "QI")])
; The first alternative is used only to compute proper length of instruction.
; Reload's algorithm does not take into account the cost of spill instructions
; needed to free register in given class, so avoid it from choosing the first
; alternative when eax is not available.
(define_insn "*movhi_1"
[(set (match_operand:HI 0 "nonimmediate_operand" "=*?a,r,r,*?a,r,m")
(match_operand:HI 1 "general_operand" "i,r,rn,rm,rm,rn"))]
[(set (match_operand:HI 0 "nonimmediate_operand" "=r,r,r,m")
(match_operand:HI 1 "general_operand" "r,rn,rm,rn"))]
"GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM"
{
switch (get_attr_type (insn))
......@@ -1341,36 +1329,35 @@
}
}
[(set (attr "type")
(cond [(and (eq_attr "alternative" "0,1")
(cond [(and (eq_attr "alternative" "0")
(ior (eq (symbol_ref "TARGET_PARTIAL_REG_STALL")
(const_int 0))
(eq (symbol_ref "TARGET_HIMODE_MATH")
(const_int 0))))
(const_string "imov")
(and (eq_attr "alternative" "2,3,4")
(and (eq_attr "alternative" "1,2")
(match_operand:HI 1 "aligned_operand" ""))
(const_string "imov")
(and (ne (symbol_ref "TARGET_MOVX")
(const_int 0))
(eq_attr "alternative" "0,1,3,4"))
(eq_attr "alternative" "0,2"))
(const_string "imovx")
]
(const_string "imov")))
(set (attr "mode")
(cond [(eq_attr "type" "imovx")
(const_string "SI")
(and (eq_attr "alternative" "2,3,4")
(and (eq_attr "alternative" "1,2")
(match_operand:HI 1 "aligned_operand" ""))
(const_string "SI")
(and (eq_attr "alternative" "0,1")
(and (eq_attr "alternative" "0")
(ior (eq (symbol_ref "TARGET_PARTIAL_REG_STALL")
(const_int 0))
(eq (symbol_ref "TARGET_HIMODE_MATH")
(const_int 0))))
(const_string "SI")
]
(const_string "HI")))
(set_attr "modrm" "0,*,*,0,*,*")])
(const_string "HI")))])
;; Stores and loads of ax to arbitrary constant address.
;; We fake an second form of instruction to force reload to load address
......
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