Add support for Cirrus EP9312, an ARM variant.

From-SVN: r62625

gcc/ChangeLog

+2003-02-10  Nick Clifton  <nickc@redhat.com>
+
+	* Contributed support for the Cirrus EP9312 "Maverick"
+	floating point co-processor.  Written by Aldy Hernandez
+	<aldyh@redhat.com>. 
+	(config/arm/arm.c): Add Cirrus support.
+	(config/arm/arm.h): Likewise.
+	(config/arm/aout.h): Likewise.
+	(config/arm/arm.md): Likewise.
+	(config/arm/arm-protos.h): Likewise.
+	(config.gcc): Likewise.
+	(doc/invoke.texi): Describe new -mcpu value and new
+	-mcirrus-fix-invalid-insns switch,
+	(cirrus.md): New file.
+
 Mon Feb 10 11:40:18 CET 2003  Jan Hubicka  <jh@suse.cz>
 
 	* combine.c (combine_simplify_rtx): Simplify using

gcc/config.gcc

@@ -259,6 +259,9 @@ strongarm*-*-*)
 arm*-*-*)
 	cpu_type=arm
 	;;
+ep9312*-*-*)
+	cpu_type=arm
+	;;
 xscale-*-*)
 	cpu_type=arm
 	;;
@@ -700,7 +703,7 @@ arm*-*-rtems*)
 	  thread_file='rtems'
 	fi
 	;;
-arm*-*-elf)
+arm*-*-elf | ep9312-*-elf)
 	tm_file="dbxelf.h elfos.h arm/unknown-elf.h arm/elf.h arm/aout.h arm/arm.h"
 	tmake_file=arm/t-arm-elf
 	;;
@@ -2789,6 +2792,7 @@ arm*-*-*)
 		| xarm7m | xarm7dm | xarm7dmi | xarm[79]tdmi \
 		| xarm7100 | xarm7500 | xarm7500fe | xarm810 \
 		| xxscale \
+		| xep9312 \
 		| xstrongarm | xstrongarm110 | xstrongarm1100)
 			target_cpu_default2="TARGET_CPU_$with_cpu"
 			;;
@@ -2806,6 +2810,11 @@ arm*-*-*)
 			fi
 			;;
 	esac
+	case $machine in
+		9ep9312-*-*)
+			target_cpu_default2="TARGET_CPU_9ep9312"
+			;;
+	esac
 	;;
 
 hppa*-*-* | parisc*-*-*)

gcc/config/arm/aout.h

@@ -73,7 +73,10 @@ Boston, MA 02111-1307, USA.  */
   "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",  \
   "r8", "r9", "sl", "fp", "ip", "sp", "lr", "pc",  \
   "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7",  \
-  "cc", "sfp", "afp"		   		   \
+  "cc", "sfp", "afp",		   		   \
+  "mv0",  "mv1",   "mv2",  "mv3",  "mv4",   "mv5", \
+  "mv6",  "mv7",   "mv8",  "mv9",  "mv10",  "mv11",\
+  "mv12", "mv13",  "mv14", "mv15"		   \
 }
 #endif
 
@@ -98,7 +101,71 @@ Boston, MA 02111-1307, USA.  */
   {"r12", 12},	/* ip */			\
   {"r13", 13},	/* sp */			\
   {"r14", 14},	/* lr */			\
-  {"r15", 15}	/* pc */			\
+  {"r15", 15},	/* pc */			\
+  {"mvf0", 27},					\
+  {"mvf1", 28},					\
+  {"mvf2", 29},					\
+  {"mvf3", 30},					\
+  {"mvf4", 31},					\
+  {"mvf5", 32},					\
+  {"mvf6", 33},					\
+  {"mvf7", 34},					\
+  {"mvf8", 35},					\
+  {"mvf9", 36},					\
+  {"mvf10", 37},				\
+  {"mvf11", 38},				\
+  {"mvf12", 39},				\
+  {"mvf13", 40},				\
+  {"mvf14", 41},				\
+  {"mvf15", 42},				\
+  {"mvd0", 27},					\
+  {"mvd1", 28},					\
+  {"mvd2", 29},					\
+  {"mvd3", 30},					\
+  {"mvd4", 31},					\
+  {"mvd5", 32},					\
+  {"mvd6", 33},					\
+  {"mvd7", 34},					\
+  {"mvd8", 35},					\
+  {"mvd9", 36},					\
+  {"mvd10", 37},				\
+  {"mvd11", 38},				\
+  {"mvd12", 39},				\
+  {"mvd13", 40},				\
+  {"mvd14", 41},				\
+  {"mvd15", 42},				\
+  {"mvfx0", 27},				\
+  {"mvfx1", 28},				\
+  {"mvfx2", 29},				\
+  {"mvfx3", 30},				\
+  {"mvfx4", 31},				\
+  {"mvfx5", 32},				\
+  {"mvfx6", 33},				\
+  {"mvfx7", 34},				\
+  {"mvfx8", 35},				\
+  {"mvfx9", 36},				\
+  {"mvfx10", 37},				\
+  {"mvfx11", 38},				\
+  {"mvfx12", 39},				\
+  {"mvfx13", 40},				\
+  {"mvfx14", 41},				\
+  {"mvfx15", 42},				\
+  {"mvdx0", 27},				\
+  {"mvdx1", 28},				\
+  {"mvdx2", 29},				\
+  {"mvdx3", 30},				\
+  {"mvdx4", 31},				\
+  {"mvdx5", 32},				\
+  {"mvdx6", 33},				\
+  {"mvdx7", 34},				\
+  {"mvdx8", 35},				\
+  {"mvdx9", 36},				\
+  {"mvdx10", 37},				\
+  {"mvdx11", 38},				\
+  {"mvdx12", 39},				\
+  {"mvdx13", 40},				\
+  {"mvdx14", 41},				\
+  {"mvdx15", 42}				\
 }
 #endif
 

gcc/config/arm/arm-protos.h

@@ -94,6 +94,11 @@ extern int    logical_binary_operator	PARAMS ((rtx, enum machine_mode));
 extern int    multi_register_push	PARAMS ((rtx, enum machine_mode));
 extern int    load_multiple_operation	PARAMS ((rtx, enum machine_mode));
 extern int    store_multiple_operation	PARAMS ((rtx, enum machine_mode));
+extern int    cirrus_fp_register	PARAMS ((rtx, enum machine_mode));
+extern int    cirrus_general_operand	PARAMS ((rtx, enum machine_mode));
+extern int    cirrus_register_operand	PARAMS ((rtx, enum machine_mode));
+extern int    cirrus_shift_const	PARAMS ((rtx, enum machine_mode));
+extern int    cirrus_memory_offset	PARAMS ((rtx));
 
 extern int    symbol_mentioned_p	PARAMS ((rtx));
 extern int    label_mentioned_p		PARAMS ((rtx));
@@ -149,7 +154,6 @@ extern rtx    arm_va_arg                PARAMS ((tree, tree));
 extern int    arm_function_arg_pass_by_reference PARAMS ((CUMULATIVE_ARGS *,
 							 enum machine_mode,
 						         tree, int));
-
 #endif
 
 #if defined AOF_ASSEMBLER 

gcc/config/arm/t-arm-elf

@@ -24,6 +24,10 @@ dp-bit.c: $(srcdir)/config/fp-bit.c
 MULTILIB_OPTIONS     = marm/mthumb
 MULTILIB_DIRNAMES    = arm thumb
 MULTILIB_EXCEPTIONS  = 
+
+# MULTILIB_OPTIONS    += mcpu=ep9312
+# MULTILIB_DIRNAMES   += ep9312
+# MULTILIB_EXCEPTIONS += *mthumb/*mcpu=ep9312*
 	
 # MULTILIB_OPTIONS     += mlittle-endian/mbig-endian
 # MULTILIB_DIRNAMES    += le be

gcc/doc/invoke.texi

@@ -386,6 +386,7 @@ in the following sections.
 -msingle-pic-base  -mno-single-pic-base @gol
 -mpic-register=@var{reg} @gol
 -mnop-fun-dllimport @gol
+-mcirrus-fix-invalid-insns -mno-cirrus-fix-invalid-insns @gol
 -mpoke-function-name @gol
 -mthumb  -marm @gol
 -mtpcs-frame  -mtpcs-leaf-frame @gol
@@ -6132,7 +6133,7 @@ assembly code.  Permissible names are: @samp{arm2}, @samp{arm250},
 @samp{strongarm}, @samp{strongarm110}, @samp{strongarm1100},
 @samp{arm8}, @samp{arm810}, @samp{arm9}, @samp{arm9e}, @samp{arm920},
 @samp{arm920t}, @samp{arm940t}, @samp{arm9tdmi}, @samp{arm10tdmi},
-@samp{arm1020t}, @samp{xscale}.
+@samp{arm1020t}, @samp{xscale}, @samp{ep9312}.
 
 @itemx -mtune=@var{name}
 @opindex mtune
@@ -6152,7 +6153,7 @@ name to determine what kind of instructions it can emit when generating
 assembly code.  This option can be used in conjunction with or instead
 of the @option{-mcpu=} option.  Permissible names are: @samp{armv2},
 @samp{armv2a}, @samp{armv3}, @samp{armv3m}, @samp{armv4}, @samp{armv4t},
-@samp{armv5}, @samp{armv5t}, @samp{armv5te}.
+@samp{armv5}, @samp{armv5t}, @samp{armv5te}, @samp{ep9312}.
 
 @item -mfpe=@var{number}
 @itemx -mfp=@var{number}
@@ -6224,6 +6225,18 @@ before execution begins.
 Specify the register to be used for PIC addressing.  The default is R10
 unless stack-checking is enabled, when R9 is used.
 
+@item -mcirrus-fix-invalid-insns
+@opindex -mcirrus-fix-invalid-insns
+@opindex -mno-cirrus-fix-invalid-insns
+Insert NOPs into the instruction stream to in order to work around
+problems with invalid Maverick instruction combinations.  This option
+is only valid if the @option{-mcpu=ep9312} option has been used to
+enable generation of instructions for the Cirrus Maverick floating
+point co-processor.  This option is not enabled by default, since the
+problem is only present in older Maverick implemenations.  The default
+can be re-enabled by use of the @option{-mno-cirrus-fix-invalid-insns}
+switch.
+
 @item -mpoke-function-name
 @opindex mpoke-function-name
 Write the name of each function into the text section, directly