[AArch64][PATCH 2/2] Combine AES instructions with xor and zero operands

gcc
2018-06-21  Andre Vieira  <andre.simoesdiasvieira@arm.com>

	* config/aarch64/aarch64-simd.md
	(*aarch64_crypto_aes<aes_op>v16qi_xor_combine): New.

gcc/testsuite
2018-06-21  Andre Vieira  <andre.simoesdiasvieira@arm.com>

	* gcc/gcc.target/aarch64/aes_xor_combine.c: New test.

From-SVN: r261836

gcc/ChangeLog

 2018-06-21  Andre Vieira  <andre.simoesdiasvieira@arm.com>
 
+	* config/aarch64/aarch64-simd.md
+	(*aarch64_crypto_aes<aes_op>v16qi_xor_combine): New.
+
+2018-06-21  Andre Vieira  <andre.simoesdiasvieira@arm.com>
+
 	* config/aarch64/aarch64-simd.md (aarch64_crypto_aes<aes_op>v16qi):
 	Make opernads of the unspec commutative.
 

gcc/config/aarch64/aarch64-simd.md

@@ -5886,6 +5886,29 @@
   [(set_attr "type" "crypto_aese")]
 )
 
+(define_insn "*aarch64_crypto_aes<aes_op>v16qi_xor_combine"
+  [(set (match_operand:V16QI 0 "register_operand" "=w")
+	(unspec:V16QI [(xor:V16QI
+			(match_operand:V16QI 1 "register_operand" "%0")
+			(match_operand:V16QI 2 "register_operand" "w"))
+		       (match_operand:V16QI 3 "aarch64_simd_imm_zero" "")]
+		       CRYPTO_AES))]
+  "TARGET_SIMD && TARGET_AES"
+  "aes<aes_op>\\t%0.16b, %2.16b"
+  [(set_attr "type" "crypto_aese")]
+)
+
+(define_insn "*aarch64_crypto_aes<aes_op>v16qi_xor_combine"
+  [(set (match_operand:V16QI 0 "register_operand" "=w")
+	(unspec:V16QI [(match_operand:V16QI 3 "aarch64_simd_imm_zero" "")
+	(xor:V16QI (match_operand:V16QI 1 "register_operand" "%0")
+		   (match_operand:V16QI 2 "register_operand" "w"))]
+	CRYPTO_AES))]
+  "TARGET_SIMD && TARGET_AES"
+  "aes<aes_op>\\t%0.16b, %2.16b"
+  [(set_attr "type" "crypto_aese")]
+)
+
 ;; When AES/AESMC fusion is enabled we want the register allocation to
 ;; look like:
 ;;    AESE Vn, _

gcc/testsuite/ChangeLog

 2018-06-21  Andre Vieira  <andre.simoesdiasvieira@arm.com>
 
+	* gcc/gcc.target/aarch64/aes_xor_combine.c: New test.
+
+2018-06-21  Andre Vieira  <andre.simoesdiasvieira@arm.com>
+
 	* gcc/gcc.target/aarch64/aes_2.c: New test.
 
 2018-06-20  Than McIntosh  <thanm@google.com>

gcc/testsuite/gcc.target/aarch64/aes_xor_combine.c

+/* { dg-do compile } */
+/* { dg-options "-O3 -mcpu=cortex-a55+crypto" } */
+#include <arm_neon.h>
+
+#define AESE(r, v, key) (r = vaeseq_u8 ((v), (key)));
+#define AESD(r, v, key) (r = vaesdq_u8 ((v), (key)));
+
+const uint8x16_t zero = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0};
+
+uint8x16_t foo0 (uint8x16_t a, uint8x16_t b)
+{
+  uint8x16_t dummy;
+  AESE(dummy, a ^ b, zero);
+  return dummy;
+}
+
+uint8x16_t foo1 (uint8x16_t a, uint8x16_t b)
+{
+  uint8x16_t dummy;
+  AESE(dummy, a ^ b, zero);
+  AESE(dummy, dummy ^ a, zero);
+  return dummy;
+}
+
+uint8x16_t bar0 (uint8x16_t a, uint8x16_t b)
+{
+  uint8x16_t dummy;
+  AESE(dummy, zero, a ^ b);
+  return dummy;
+}
+
+uint8x16_t bar1 (uint8x16_t a, uint8x16_t b)
+{
+  uint8x16_t dummy;
+  AESE(dummy, zero, a ^ b);
+  AESE(dummy, zero, b ^ dummy);
+  return dummy;
+}
+
+uint8x16_t foo2 (uint8x16_t a, uint8x16_t b)
+{
+  uint8x16_t dummy;
+  AESD(dummy, a ^ b, zero);
+  return dummy;
+}
+
+uint8x16_t foo3 (uint8x16_t a, uint8x16_t b)
+{
+  uint8x16_t dummy;
+  AESD(dummy, a ^ b, zero);
+  AESD(dummy, dummy ^ a, zero);
+  return dummy;
+}
+
+uint8x16_t bar2 (uint8x16_t a, uint8x16_t b)
+{
+  uint8x16_t dummy;
+  AESD(dummy, zero, a ^ b);
+  return dummy;
+}
+
+uint8x16_t bar3 (uint8x16_t a, uint8x16_t b)
+{
+  uint8x16_t dummy;
+  AESD(dummy, zero, a ^ b);
+  AESD(dummy, zero, b ^ dummy);
+  return dummy;
+}
+/* { dg-final { scan-assembler-not "eor" } } */
+/* { dg-final { scan-assembler-not "mov" } } */