Skip to content

R
riscv-gcc-1
Commit 9b2e34ef by Christophe Lyon Committed by Christophe Lyon
Options

[ARM] Use __ARM_ARCH and __ARM_FEATURE_LDREX instead of __ARM_ARCH__ 

2018-06-21  Christophe Lyon  <christophe.lyon@linaro.org>

	libatomic/
	* config/arm/arm-config.h (__ARM_ARCH__): Remove definitions, use
	__ARM_ARCH instead. Use __ARM_FEATURE_LDREX to define HAVE_STREX
	and HAVE_STREXBHD

	libgcc/
	* config/arm/lib1funcs.S (__ARM_ARCH__): Remove definitions, use
	__ARM_ARCH and __ARM_FEATURE_CLZ instead.
	(HAVE_ARM_CLZ): Remove definition, use __ARM_FEATURE_CLZ instead.
	* config/arm/ieee754-df.S: Use __ARM_FEATURE_CLZ instead of
	__ARM_ARCH__.
	* config/arm/ieee754-sf.S: Likewise.
	* config/arm/libunwind.S: Use __ARM_ARCH instead of __ARM_ARCH__.

From-SVN: r261841
parent d1b0dd54
Showing with 48 additions and 124 deletions
libatomic/ChangeLog
2018-06-21 Christophe Lyon <christophe.lyon@linaro.org>
* config/arm/arm-config.h (__ARM_ARCH__): Remove definitions, use
__ARM_ARCH instead. Use __ARM_FEATURE_LDREX to define HAVE_STREX
and HAVE_STREXBHD
2018-05-23 Florian Weimer <fweimer@redhat.com> 2018-05-23 Florian Weimer <fweimer@redhat.com>
PR libgcc/60790 PR libgcc/60790
......
libatomic/config/arm/arm-config.h
...@@ -23,57 +23,15 @@ ...@@ -23,57 +23,15 @@
<http://www.gnu.org/licenses/>. */ <http://www.gnu.org/licenses/>. */
#if defined(__ARM_ARCH_2__) #if __ARM_FEATURE_LDREX & 4
# define __ARM_ARCH__ 2
#endif
#if defined(__ARM_ARCH_3__)
# define __ARM_ARCH__ 3
#endif
#if defined(__ARM_ARCH_3M__) || defined(__ARM_ARCH_4__) \
|| defined(__ARM_ARCH_4T__)
/* We use __ARM_ARCH__ set to 4 here, but in reality it's any processor with
long multiply instructions. That includes v3M. */
# define __ARM_ARCH__ 4
#endif
#if defined(__ARM_ARCH_5__) || defined(__ARM_ARCH_5T__) \
|| defined(__ARM_ARCH_5E__) || defined(__ARM_ARCH_5TE__) \
|| defined(__ARM_ARCH_5TEJ__)
# define __ARM_ARCH__ 5
#endif
#if defined(__ARM_ARCH_6__) || defined(__ARM_ARCH_6J__) \
|| defined(__ARM_ARCH_6K__) || defined(__ARM_ARCH_6Z__) \
|| defined(__ARM_ARCH_6ZK__) || defined(__ARM_ARCH_6T2__) \
|| defined(__ARM_ARCH_6M__)
# define __ARM_ARCH__ 6
#endif
#if defined(__ARM_ARCH_7__) || defined(__ARM_ARCH_7A__) \
|| defined(__ARM_ARCH_7R__) || defined(__ARM_ARCH_7M__) \
|| defined(__ARM_ARCH_7EM__)
# define __ARM_ARCH__ 7
#endif
#if defined(__ARM_ARCH_8A__)
# define __ARM_ARCH__ 8
#endif
#ifndef __ARM_ARCH__
#error Unable to determine architecture.
#endif
#if __ARM_ARCH__ >= 7 || defined(__ARM_ARCH_6K__) || defined(__ARM_ARCH_6ZK__)
# define HAVE_STREX 1 # define HAVE_STREX 1
#endif
#if (__ARM_FEATURE_LDREX & 0xF) == 0xF
# define HAVE_STREXBHD 1 # define HAVE_STREXBHD 1
#elif __ARM_ARCH__ == 6
# define HAVE_STREX 1
#endif #endif
#if __ARM_ARCH__ >= 7 #if __ARM_ARCH >= 7
# define HAVE_DMB 1 # define HAVE_DMB 1
#elif __ARM_ARCH__ == 6 #elif __ARM_ARCH == 6
# define HAVE_DMB_MCR 1 # define HAVE_DMB_MCR 1
#endif #endif
libgcc/ChangeLog
2018-06-21 Christophe Lyon <christophe.lyon@linaro.org> 2018-06-21 Christophe Lyon <christophe.lyon@linaro.org>
* config/arm/lib1funcs.S (__ARM_ARCH__): Remove definitions, use
__ARM_ARCH and __ARM_FEATURE_CLZ instead.
(HAVE_ARM_CLZ): Remove definition, use __ARM_FEATURE_CLZ instead.
* config/arm/ieee754-df.S: Use __ARM_FEATURE_CLZ instead of
__ARM_ARCH__.
* config/arm/ieee754-sf.S: Likewise.
* config/arm/libunwind.S: Use __ARM_ARCH instead of __ARM_ARCH__.
2018-06-21 Christophe Lyon <christophe.lyon@linaro.org>
* config/arm/ieee754-df.S: Remove code for __ARM_ARCH__ < 4, no * config/arm/ieee754-df.S: Remove code for __ARM_ARCH__ < 4, no
longer supported. longer supported.
* config/arm/ieee754-sf.S: Likewise. * config/arm/ieee754-sf.S: Likewise.
......
libgcc/config/arm/ieee754-df.S
...@@ -245,7 +245,7 @@ LSYM(Lad_a): ...@@ -245,7 +245,7 @@ LSYM(Lad_a):
@ No rounding necessary since ip will always be 0 at this point. @ No rounding necessary since ip will always be 0 at this point.
LSYM(Lad_l): LSYM(Lad_l):
#if __ARM_ARCH__ < 5 #if !defined (__ARM_FEATURE_CLZ)
teq xh, #0 teq xh, #0
movne r3, #20 movne r3, #20
......
libgcc/config/arm/ieee754-sf.S
...@@ -175,7 +175,7 @@ LSYM(Lad_a): ...@@ -175,7 +175,7 @@ LSYM(Lad_a):
@ No rounding necessary since r1 will always be 0 at this point. @ No rounding necessary since r1 will always be 0 at this point.
LSYM(Lad_l): LSYM(Lad_l):
#if __ARM_ARCH__ < 5 #if !defined (__ARM_FEATURE_CLZ)
movs ip, r0, lsr #12 movs ip, r0, lsr #12
moveq r0, r0, lsl #12 moveq r0, r0, lsl #12
...@@ -370,7 +370,7 @@ ARM_FUNC_ALIAS aeabi_l2f floatdisf ...@@ -370,7 +370,7 @@ ARM_FUNC_ALIAS aeabi_l2f floatdisf
subeq r3, r3, #(32 << 23) subeq r3, r3, #(32 << 23)
2: sub r3, r3, #(1 << 23) 2: sub r3, r3, #(1 << 23)
#if __ARM_ARCH__ < 5 #if !defined (__ARM_FEATURE_CLZ)
mov r2, #23 mov r2, #23
cmp ip, #(1 << 16) cmp ip, #(1 << 16)
......
libgcc/config/arm/lib1funcs.S
...@@ -74,49 +74,6 @@ see the files COPYING3 and COPYING.RUNTIME respectively. If not, see ...@@ -74,49 +74,6 @@ see the files COPYING3 and COPYING.RUNTIME respectively. If not, see
/* Function end macros. Variants for interworking. */ /* Function end macros. Variants for interworking. */
#if defined(__ARM_ARCH_2__)
# define __ARM_ARCH__ 2
#endif
#if defined(__ARM_ARCH_3__)
# define __ARM_ARCH__ 3
#endif
#if defined(__ARM_ARCH_3M__) || defined(__ARM_ARCH_4__) \
|| defined(__ARM_ARCH_4T__)
/* We use __ARM_ARCH__ set to 4 here, but in reality it's any processor with
long multiply instructions. That includes v3M. */
# define __ARM_ARCH__ 4
#endif
#if defined(__ARM_ARCH_5__) || defined(__ARM_ARCH_5T__) \
|| defined(__ARM_ARCH_5E__) || defined(__ARM_ARCH_5TE__) \
|| defined(__ARM_ARCH_5TEJ__)
# define __ARM_ARCH__ 5
#endif
#if defined(__ARM_ARCH_6__) || defined(__ARM_ARCH_6J__) \
|| defined(__ARM_ARCH_6K__) || defined(__ARM_ARCH_6Z__) \
|| defined(__ARM_ARCH_6ZK__) || defined(__ARM_ARCH_6T2__) \
|| defined(__ARM_ARCH_6M__)
# define __ARM_ARCH__ 6
#endif
#if defined(__ARM_ARCH_7__) || defined(__ARM_ARCH_7A__) \
|| defined(__ARM_ARCH_7R__) || defined(__ARM_ARCH_7M__) \
|| defined(__ARM_ARCH_7EM__)
# define __ARM_ARCH__ 7
#endif
#if defined(__ARM_ARCH_8A__) || defined(__ARM_ARCH_8M_BASE__) \
|| defined(__ARM_ARCH_8M_MAIN__) || defined(__ARM_ARCH_8R__)
# define __ARM_ARCH__ 8
#endif
#ifndef __ARM_ARCH__
#error Unable to determine architecture.
#endif
/* There are times when we might prefer Thumb1 code even if ARM code is /* There are times when we might prefer Thumb1 code even if ARM code is
permitted, for example, the code might be smaller, or there might be permitted, for example, the code might be smaller, or there might be
interworking problems with switching to ARM state if interworking is interworking problems with switching to ARM state if interworking is
...@@ -135,13 +92,13 @@ see the files COPYING3 and COPYING.RUNTIME respectively. If not, see ...@@ -135,13 +92,13 @@ see the files COPYING3 and COPYING.RUNTIME respectively. If not, see
/* How to return from a function call depends on the architecture variant. */ /* How to return from a function call depends on the architecture variant. */
#if (__ARM_ARCH__ > 4) || defined(__ARM_ARCH_4T__) #if (__ARM_ARCH > 4) || defined(__ARM_ARCH_4T__)
# define RET bx lr # define RET bx lr
# define RETc(x) bx##x lr # define RETc(x) bx##x lr
/* Special precautions for interworking on armv4t. */ /* Special precautions for interworking on armv4t. */
# if (__ARM_ARCH__ == 4) # if (__ARM_ARCH == 4)
/* Always use bx, not ldr pc. */ /* Always use bx, not ldr pc. */
# if (defined(__thumb__) || defined(__THUMB_INTERWORK__)) # if (defined(__thumb__) || defined(__THUMB_INTERWORK__))
...@@ -544,7 +501,7 @@ pc .req r15 ...@@ -544,7 +501,7 @@ pc .req r15
/* ------------------------------------------------------------------------ */ /* ------------------------------------------------------------------------ */
.macro ARM_DIV_BODY dividend, divisor, result, curbit .macro ARM_DIV_BODY dividend, divisor, result, curbit
#if __ARM_ARCH__ >= 5 && ! defined (__OPTIMIZE_SIZE__) #if defined (__ARM_FEATURE_CLZ) && ! defined (__OPTIMIZE_SIZE__)
#if defined (__thumb2__) #if defined (__thumb2__)
clz \curbit, \dividend clz \curbit, \dividend
...@@ -584,8 +541,8 @@ pc .req r15 ...@@ -584,8 +541,8 @@ pc .req r15
.endr .endr
#endif #endif
#else /* __ARM_ARCH__ < 5 || defined (__OPTIMIZE_SIZE__) */ #else /* !defined (__ARM_FEATURE_CLZ) || defined (__OPTIMIZE_SIZE__) */
#if __ARM_ARCH__ >= 5 #if defined (__ARM_FEATURE_CLZ)
clz \curbit, \divisor clz \curbit, \divisor
clz \result, \dividend clz \result, \dividend
...@@ -595,7 +552,7 @@ pc .req r15 ...@@ -595,7 +552,7 @@ pc .req r15
mov \curbit, \curbit, lsl \result mov \curbit, \curbit, lsl \result
mov \result, #0 mov \result, #0
#else /* __ARM_ARCH__ < 5 */ #else /* !defined (__ARM_FEATURE_CLZ) */
@ Initially shift the divisor left 3 bits if possible, @ Initially shift the divisor left 3 bits if possible,
@ set curbit accordingly. This allows for curbit to be located @ set curbit accordingly. This allows for curbit to be located
...@@ -626,7 +583,7 @@ pc .req r15 ...@@ -626,7 +583,7 @@ pc .req r15
mov \result, #0 mov \result, #0
#endif /* __ARM_ARCH__ < 5 */ #endif /* !defined (__ARM_FEATURE_CLZ) */
@ Division loop @ Division loop
1: cmp \dividend, \divisor 1: cmp \dividend, \divisor
...@@ -651,13 +608,13 @@ pc .req r15 ...@@ -651,13 +608,13 @@ pc .req r15
movne \divisor, \divisor, lsr #4 movne \divisor, \divisor, lsr #4
bne 1b bne 1b
#endif /* __ARM_ARCH__ < 5 || defined (__OPTIMIZE_SIZE__) */ #endif /* !defined (__ARM_FEATURE_CLZ) || defined (__OPTIMIZE_SIZE__) */
.endm .endm
/* ------------------------------------------------------------------------ */ /* ------------------------------------------------------------------------ */
.macro ARM_DIV2_ORDER divisor, order .macro ARM_DIV2_ORDER divisor, order
#if __ARM_ARCH__ >= 5 #if defined (__ARM_FEATURE_CLZ)
clz \order, \divisor clz \order, \divisor
rsb \order, \order, #31 rsb \order, \order, #31
...@@ -687,7 +644,7 @@ pc .req r15 ...@@ -687,7 +644,7 @@ pc .req r15
/* ------------------------------------------------------------------------ */ /* ------------------------------------------------------------------------ */
.macro ARM_MOD_BODY dividend, divisor, order, spare .macro ARM_MOD_BODY dividend, divisor, order, spare
#if __ARM_ARCH__ >= 5 && ! defined (__OPTIMIZE_SIZE__) #if defined(__ARM_FEATURE_CLZ) && ! defined (__OPTIMIZE_SIZE__)
clz \order, \divisor clz \order, \divisor
clz \spare, \dividend clz \spare, \dividend
...@@ -702,15 +659,15 @@ pc .req r15 ...@@ -702,15 +659,15 @@ pc .req r15
subcs \dividend, \dividend, \divisor, lsl #shift subcs \dividend, \dividend, \divisor, lsl #shift
.endr .endr
#else /* __ARM_ARCH__ < 5 || defined (__OPTIMIZE_SIZE__) */ #else /* !defined (__ARM_FEATURE_CLZ) || defined (__OPTIMIZE_SIZE__) */
#if __ARM_ARCH__ >= 5 #if defined (__ARM_FEATURE_CLZ)
clz \order, \divisor clz \order, \divisor
clz \spare, \dividend clz \spare, \dividend
sub \order, \order, \spare sub \order, \order, \spare
mov \divisor, \divisor, lsl \order mov \divisor, \divisor, lsl \order
#else /* __ARM_ARCH__ < 5 */ #else /* !defined (__ARM_FEATURE_CLZ) */
mov \order, #0 mov \order, #0
...@@ -732,7 +689,7 @@ pc .req r15 ...@@ -732,7 +689,7 @@ pc .req r15
addlo \order, \order, #1 addlo \order, \order, #1
blo 1b blo 1b
#endif /* __ARM_ARCH__ < 5 */ #endif /* !defined (__ARM_FEATURE_CLZ) */
@ Perform all needed substractions to keep only the reminder. @ Perform all needed substractions to keep only the reminder.
@ Do comparisons in batch of 4 first. @ Do comparisons in batch of 4 first.
...@@ -770,7 +727,7 @@ pc .req r15 ...@@ -770,7 +727,7 @@ pc .req r15
subhs \dividend, \dividend, \divisor subhs \dividend, \dividend, \divisor
5: 5:
#endif /* __ARM_ARCH__ < 5 || defined (__OPTIMIZE_SIZE__) */ #endif /* !defined (__ARM_FEATURE_CLZ) || defined (__OPTIMIZE_SIZE__) */
.endm .endm
/* ------------------------------------------------------------------------ */ /* ------------------------------------------------------------------------ */
...@@ -1560,7 +1517,7 @@ LSYM(Lover12): ...@@ -1560,7 +1517,7 @@ LSYM(Lover12):
@ EABI GNU/Linux call to cacheflush syscall. @ EABI GNU/Linux call to cacheflush syscall.
ARM_FUNC_START clear_cache ARM_FUNC_START clear_cache
do_push {r7} do_push {r7}
#if __ARM_ARCH__ >= 7 || defined(__ARM_ARCH_6T2__) #if __ARM_ARCH >= 7 || defined(__ARM_ARCH_6T2__)
movw r7, #2 movw r7, #2
movt r7, #0xf movt r7, #0xf
#else #else
...@@ -1699,13 +1656,6 @@ LSYM(Lover12): ...@@ -1699,13 +1656,6 @@ LSYM(Lover12):
#endif /* __symbian__ */ #endif /* __symbian__ */
#if (__ARM_ARCH_ISA_THUMB == 2 \
|| (__ARM_ARCH_ISA_ARM \
&& (__ARM_ARCH__ > 5 \
|| (__ARM_ARCH__ == 5 && __ARM_ARCH_ISA_THUMB))))
#define HAVE_ARM_CLZ 1
#endif
#ifdef L_clzsi2 #ifdef L_clzsi2
#ifdef NOT_ISA_TARGET_32BIT #ifdef NOT_ISA_TARGET_32BIT
FUNC_START clzsi2 FUNC_START clzsi2
...@@ -1736,7 +1686,7 @@ FUNC_START clzsi2 ...@@ -1736,7 +1686,7 @@ FUNC_START clzsi2
FUNC_END clzsi2 FUNC_END clzsi2
#else #else
ARM_FUNC_START clzsi2 ARM_FUNC_START clzsi2
# if defined(HAVE_ARM_CLZ) # if defined (__ARM_FEATURE_CLZ)
clz r0, r0 clz r0, r0
RET RET
# else # else
...@@ -1760,13 +1710,13 @@ ARM_FUNC_START clzsi2 ...@@ -1760,13 +1710,13 @@ ARM_FUNC_START clzsi2
.align 2 .align 2
1: 1:
.byte 4, 3, 2, 2, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0 .byte 4, 3, 2, 2, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0
# endif /* !HAVE_ARM_CLZ */ # endif /* !defined (__ARM_FEATURE_CLZ) */
FUNC_END clzsi2 FUNC_END clzsi2
#endif #endif
#endif /* L_clzsi2 */ #endif /* L_clzsi2 */
#ifdef L_clzdi2 #ifdef L_clzdi2
#if !defined(HAVE_ARM_CLZ) #if !defined (__ARM_FEATURE_CLZ)
# ifdef NOT_ISA_TARGET_32BIT # ifdef NOT_ISA_TARGET_32BIT
FUNC_START clzdi2 FUNC_START clzdi2
...@@ -1800,7 +1750,7 @@ ARM_FUNC_START clzdi2 ...@@ -1800,7 +1750,7 @@ ARM_FUNC_START clzdi2
# endif # endif
FUNC_END clzdi2 FUNC_END clzdi2
#else /* HAVE_ARM_CLZ */ #else /* defined (__ARM_FEATURE_CLZ) */
ARM_FUNC_START clzdi2 ARM_FUNC_START clzdi2
cmp xxh, #0 cmp xxh, #0
...@@ -1848,7 +1798,7 @@ FUNC_START ctzsi2 ...@@ -1848,7 +1798,7 @@ FUNC_START ctzsi2
ARM_FUNC_START ctzsi2 ARM_FUNC_START ctzsi2
rsb r1, r0, #0 rsb r1, r0, #0
and r0, r0, r1 and r0, r0, r1
# if defined(HAVE_ARM_CLZ) # if defined (__ARM_FEATURE_CLZ)
clz r0, r0 clz r0, r0
rsb r0, r0, #31 rsb r0, r0, #31
RET RET
...@@ -1873,7 +1823,7 @@ ARM_FUNC_START ctzsi2 ...@@ -1873,7 +1823,7 @@ ARM_FUNC_START ctzsi2
.align 2 .align 2
1: 1:
.byte 27, 28, 29, 29, 30, 30, 30, 30, 31, 31, 31, 31, 31, 31, 31, 31 .byte 27, 28, 29, 29, 30, 30, 30, 30, 31, 31, 31, 31, 31, 31, 31, 31
# endif /* !HAVE_ARM_CLZ */ # endif /* !defined (__ARM_FEATURE_CLZ) */
FUNC_END ctzsi2 FUNC_END ctzsi2
#endif #endif
#endif /* L_clzsi2 */ #endif /* L_clzsi2 */
...@@ -1887,7 +1837,7 @@ ARM_FUNC_START ctzsi2 ...@@ -1887,7 +1837,7 @@ ARM_FUNC_START ctzsi2
not support Thumb instructions. (This can be a multilib option). */ not support Thumb instructions. (This can be a multilib option). */
#if defined __ARM_ARCH_4T__ || defined __ARM_ARCH_5T__\ #if defined __ARM_ARCH_4T__ || defined __ARM_ARCH_5T__\
|| defined __ARM_ARCH_5TE__ || defined __ARM_ARCH_5TEJ__ \ || defined __ARM_ARCH_5TE__ || defined __ARM_ARCH_5TEJ__ \
|| __ARM_ARCH__ >= 6 || __ARM_ARCH >= 6
#if defined L_call_via_rX #if defined L_call_via_rX
......
libgcc/config/arm/libunwind.S
...@@ -46,7 +46,7 @@ ...@@ -46,7 +46,7 @@
EQUIV SYM (\name), SYM (__\name) EQUIV SYM (\name), SYM (__\name)
.endm .endm
#if (__ARM_ARCH__ == 4) #if (__ARM_ARCH == 4)
/* Some coprocessors require armv5t. We know this code will never be run on /* Some coprocessors require armv5t. We know this code will never be run on
other cpus. Tell gas to allow armv5t, but only mark the objects as armv4. other cpus. Tell gas to allow armv5t, but only mark the objects as armv4.
*/ */
......
Markdown is supported
0% or
You are about to add 0 people to the discussion. Proceed with caution.
Finish editing this message first!
Please register or to comment