[ARM][1/3] Add rev field to rtx cost tables

       * config/arm/aarch-common-protos.h (alu_cost_table): Add rev field.
       * config/arm/aarch-cost-tables.h (generic_extra_costs): Specify
       rev cost.
       (cortex_a53_extra_costs): Likewise.
       (cortex_a57_extra_costs): Likewise.
       * config/arm/arm.c (cortexa9_extra_costs): Likewise.
       (cortexa7_extra_costs): Likewise.
       (cortexa8_extra_costs): Likewise.
       (cortexa12_extra_costs): Likewise.
       (cortexa15_extra_costs): Likewise.
       (v7m_extra_costs): Likewise.
       (arm_new_rtx_costs): Handle BSWAP.

From-SVN: r209703

gcc/ChangeLog

+2014-04-23  Kyrylo Tkachov  <kyrylo.tkachov@arm.com>
+
+       * config/arm/aarch-common-protos.h (alu_cost_table): Add rev field.
+       * config/arm/aarch-cost-tables.h (generic_extra_costs): Specify
+       rev cost.
+       (cortex_a53_extra_costs): Likewise.
+       (cortex_a57_extra_costs): Likewise.
+       * config/arm/arm.c (cortexa9_extra_costs): Likewise.
+       (cortexa7_extra_costs): Likewise.
+       (cortexa8_extra_costs): Likewise.
+       (cortexa12_extra_costs): Likewise.
+       (cortexa15_extra_costs): Likewise.
+       (v7m_extra_costs): Likewise.
+       (arm_new_rtx_costs): Handle BSWAP.
+
 2013-04-23  Kyrylo Tkachov  <kyrylo.tkachov@arm.com>
 
        * config/arm/arm.c (cortexa8_extra_costs): New table.

gcc/config/arm/aarch-common-protos.h

@@ -54,6 +54,7 @@ struct alu_cost_table
   const int bfi;		/* Bit-field insert.  */
   const int bfx;		/* Bit-field extraction.  */
   const int clz;		/* Count Leading Zeros.  */
+  const int rev;		/* Reverse bits/bytes.  */
   const int non_exec;		/* Extra cost when not executing insn.  */
   const bool non_exec_costs_exec; /* True if non-execution must add the exec
 				     cost.  */

gcc/config/arm/aarch-cost-tables.h

@@ -39,6 +39,7 @@ const struct cpu_cost_table generic_extra_costs =
     0,			/* bfi.  */
     0,			/* bfx.  */
     0,			/* clz.  */
+    0,			/* rev.  */
     COSTS_N_INSNS (1),	/* non_exec.  */
     false		/* non_exec_costs_exec.  */
   },
@@ -139,6 +140,7 @@ const struct cpu_cost_table cortexa53_extra_costs =
     COSTS_N_INSNS (1),	/* bfi.  */
     COSTS_N_INSNS (1),	/* bfx.  */
     0,			/* clz.  */
+    0,			/* rev.  */
     0,			/* non_exec.  */
     true		/* non_exec_costs_exec.  */
   },
@@ -239,6 +241,7 @@ const struct cpu_cost_table cortexa57_extra_costs =
     COSTS_N_INSNS (1), /* bfi.  */
     0,                 /* bfx.  */
     0,                 /* clz.  */
+    0,			/* rev.  */
     0,                 /* non_exec.  */
     true               /* non_exec_costs_exec.  */
   },

gcc/config/arm/arm.c

@@ -986,6 +986,7 @@ const struct cpu_cost_table cortexa9_extra_costs =
     COSTS_N_INSNS (1),	/* bfi.  */
     COSTS_N_INSNS (1),	/* bfx.  */
     0,			/* clz.  */
+    0,			/* rev.  */
     0,			/* non_exec.  */
     true		/* non_exec_costs_exec.  */
   },
@@ -1086,6 +1087,7 @@ const struct cpu_cost_table cortexa8_extra_costs =
     0,			/* bfi.  */
     0,			/* bfx.  */
     0,			/* clz.  */
+    0,			/* rev.  */
     0,			/* non_exec.  */
     true		/* non_exec_costs_exec.  */
   },
@@ -1188,6 +1190,7 @@ const struct cpu_cost_table cortexa7_extra_costs =
     COSTS_N_INSNS (1),	/* bfi.  */
     COSTS_N_INSNS (1),	/* bfx.  */
     COSTS_N_INSNS (1),	/* clz.  */
+    COSTS_N_INSNS (1),	/* rev.  */
     0,			/* non_exec.  */
     true		/* non_exec_costs_exec.  */
   },
@@ -1289,6 +1292,7 @@ const struct cpu_cost_table cortexa12_extra_costs =
     0,			/* bfi.  */
     COSTS_N_INSNS (1),	/* bfx.  */
     COSTS_N_INSNS (1),	/* clz.  */
+    COSTS_N_INSNS (1),	/* rev.  */
     0,			/* non_exec.  */
     true		/* non_exec_costs_exec.  */
   },
@@ -1389,6 +1393,7 @@ const struct cpu_cost_table cortexa15_extra_costs =
     COSTS_N_INSNS (1),	/* bfi.  */
     0,			/* bfx.  */
     0,			/* clz.  */
+    0,			/* rev.  */
     0,			/* non_exec.  */
     true		/* non_exec_costs_exec.  */
   },
@@ -1489,6 +1494,7 @@ const struct cpu_cost_table v7m_extra_costs =
     0,			/* bfi.  */
     0,			/* bfx.  */
     0,			/* clz.  */
+    0,			/* rev.  */
     COSTS_N_INSNS (1),	/* non_exec.  */
     false		/* non_exec_costs_exec.  */
   },
@@ -9470,6 +9476,47 @@ arm_new_rtx_costs (rtx x, enum rtx_code code, enum rtx_code outer_code,
       *cost = LIBCALL_COST (2);
       return false;
 
+    case BSWAP:
+      if (arm_arch6)
+        {
+          if (mode == SImode)
+            {
+              *cost = COSTS_N_INSNS (1);
+              if (speed_p)
+                *cost += extra_cost->alu.rev;
+
+              return false;
+            }
+        }
+      else
+        {
+        /* No rev instruction available.  Look at arm_legacy_rev
+           and thumb_legacy_rev for the form of RTL used then.  */
+          if (TARGET_THUMB)
+            {
+              *cost = COSTS_N_INSNS (10);
+
+              if (speed_p)
+                {
+                  *cost += 6 * extra_cost->alu.shift;
+                  *cost += 3 * extra_cost->alu.logical;
+                }
+            }
+          else
+            {
+              *cost = COSTS_N_INSNS (5);
+
+              if (speed_p)
+                {
+                  *cost += 2 * extra_cost->alu.shift;
+                  *cost += extra_cost->alu.arith_shift;
+                  *cost += 2 * extra_cost->alu.logical;
+                }
+            }
+          return true;
+        }
+      return false;
+
     case MINUS:
       if (TARGET_HARD_FLOAT && GET_MODE_CLASS (mode) == MODE_FLOAT
 	  && (mode == SFmode || !TARGET_VFP_SINGLE))