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riscv-gcc-1
Commit 9a63901f by Richard Kenner
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Use WORD_REGISTER_OPERATION and LOAD_EXTEND_OP and delete 

BYTE_LOADS_{SIGN,ZERO}_EXTEND.

From-SVN: r5477
parent e90d3cbb
Showing with 100 additions and 47 deletions
gcc/config/a29k/a29k.h
......@@ -1204,9 +1204,15 @@ extern char *a29k_function_name;
manipulate fields. */
#define SLOW_BYTE_ACCESS 0
/* Define if normal loads of shorter-than-word items from memory clears
the rest of the bigs in the register. */
#define BYTE_LOADS_ZERO_EXTEND
/* Define if operations between registers always perform the operation
on the full register even if a narrower mode is specified. */
#define WORD_REGISTER_OPERATIONS
/* Define if loading in MODE, an integral mode narrower than BITS_PER_WORD
will either zero-extend or sign-extend. The value of this macro should
be the code that says which one of the two operations is implicitly
done, NIL if none. */
#define LOAD_EXTEND_OP(MODE) ZERO_EXTEND
/* Define if the object format being used is COFF or a superset. */
#define OBJECT_FORMAT_COFF
......
gcc/config/alpha/alpha.h
......@@ -1221,13 +1221,15 @@ extern char *current_function_name;
#define SLOW_BYTE_ACCESS 1
/* Define if normal loads of shorter-than-word items from memory clears
the rest of the bits in the register. */
/* #define BYTE_LOADS_ZERO_EXTEND */
/* Define if normal loads of shorter-than-word items from memory sign-extends
the rest of the bits in the register. */
#define BYTE_LOADS_SIGN_EXTEND
/* Define if operations between registers always perform the operation
on the full register even if a narrower mode is specified. */
#define WORD_REGISTER_OPERATIONS
/* Define if loading in MODE, an integral mode narrower than BITS_PER_WORD
will either zero-extend or sign-extend. The value of this macro should
be the code that says which one of the two operations is implicitly
done, NIL if none. */
#define LOAD_EXTEND_OP(MODE) SIGN_EXTEND
/* Define if loading short immediate values into registers sign extends. */
#define SHORT_IMMEDIATES_SIGN_EXTEND
......
gcc/config/arm/arm.h
/* Definitions of target machine for GNU compiler, for Acorn RISC Machine.
Copyright (C) 1991 Free Software Foundation, Inc.
Copyright (C) 1991, 1993 Free Software Foundation, Inc.
Contributed by Pieter `Tiggr' Schoenmakers (rcpieter@win.tue.nl)
and Martin Simmons (@harleqn.co.uk).
......@@ -848,11 +848,6 @@ do \
in one reasonably fast instruction. */
#define MOVE_MAX 4
/* Define if normal loads of shorter-than-word items from memory clears
the rest of the bigs in the register.
On the ARM, movhi does a garbage extend. */
/* #define BYTE_LOADS_ZERO_EXTEND */
/* Define this if zero-extension is slow (more than one real instruction).
On the ARM, it is more than one instruction only if not fetching from
memory. */
......
gcc/config/clipper/clipper.h
......@@ -773,10 +773,15 @@ do \
jumps to the default label instead. */
/* #define CASE_DROPS_THROUGH */
/* Define this macro if an instruction to load a value narrower than a
word from memory into a register also sign-extends the value to
the whole register. */
#define BYTE_LOADS_SIGN_EXTEND
/* Define if operations between registers always perform the operation
on the full register even if a narrower mode is specified. */
#define WORD_REGISTER_OPERATIONS
/* Define if loading in MODE, an integral mode narrower than BITS_PER_WORD
will either zero-extend or sign-extend. The value of this macro should
be the code that says which one of the two operations is implicitly
done, NIL if none. */
#define LOAD_EXTEND_OP(MODE) SIGN_EXTEND
/* Specify the tree operation to be used to convert reals to integers. */
#define IMPLICIT_FIX_EXPR FIX_ROUND_EXPR
......
gcc/config/i960/i960.h
......@@ -1055,9 +1055,15 @@ extern struct rtx_def *legitimize_address ();
in one reasonably fast instruction. */
#define MOVE_MAX 16
/* Define if normal loads of shorter-than-word items from memory clears
the rest of the bigs in the register. */
#define BYTE_LOADS_ZERO_EXTEND
/* Define if operations between registers always perform the operation
on the full register even if a narrower mode is specified. */
#define WORD_REGISTER_OPERATIONS
/* Define if loading in MODE, an integral mode narrower than BITS_PER_WORD
will either zero-extend or sign-extend. The value of this macro should
be the code that says which one of the two operations is implicitly
done, NIL if none. */
#define LOAD_EXTEND_OP(MODE) ZERO_EXTEND
/* Nonzero if access to memory by bytes is no faster than for words.
Defining this results in worse code on the i960. */
......
gcc/config/m88k/m88k.h
......@@ -1508,9 +1508,15 @@ enum reg_class { NO_REGS, AP_REG, XRF_REGS, GENERAL_REGS, AGRF_REGS,
in one reasonably fast instruction. */
#define MOVE_MAX 8
/* Define if normal loads of shorter-than-word items from memory clears
the rest of the bigs in the register. */
#define BYTE_LOADS_ZERO_EXTEND
/* Define if operations between registers always perform the operation
on the full register even if a narrower mode is specified. */
#define WORD_REGISTER_OPERATIONS
/* Define if loading in MODE, an integral mode narrower than BITS_PER_WORD
will either zero-extend or sign-extend. The value of this macro should
be the code that says which one of the two operations is implicitly
done, NIL if none. */
#define LOAD_EXTEND_OP(MODE) ZERO_EXTEND
/* Zero if access to memory by bytes is faster. */
#define SLOW_BYTE_ACCESS 1
......
gcc/config/mips/mips.h
......@@ -1049,12 +1049,15 @@ do { \
#define PROMOTE_PROTOTYPES
/* Define this macro if an instruction to load a value narrower
than a word from memory into a register also zero-extends the
value to the whole register. */
#define BYTE_LOADS_ZERO_EXTEND
/* Define if operations between registers always perform the operation
on the full register even if a narrower mode is specified. */
#define WORD_REGISTER_OPERATIONS
/* Define if loading in MODE, an integral mode narrower than BITS_PER_WORD
will either zero-extend or sign-extend. The value of this macro should
be the code that says which one of the two operations is implicitly
done, NIL if none. */
#define LOAD_EXTEND_OP(MODE) ZERO_EXTEND
/* Standard register usage. */
......
gcc/config/pa/pa.h
......@@ -1367,9 +1367,15 @@ while (0)
in one reasonably fast instruction. */
#define MOVE_MAX 8
/* Define if normal loads of shorter-than-word items from memory clears
the rest of the bigs in the register. */
#define BYTE_LOADS_ZERO_EXTEND
/* Define if operations between registers always perform the operation
on the full register even if a narrower mode is specified. */
#define WORD_REGISTER_OPERATIONS
/* Define if loading in MODE, an integral mode narrower than BITS_PER_WORD
will either zero-extend or sign-extend. The value of this macro should
be the code that says which one of the two operations is implicitly
done, NIL if none. */
#define LOAD_EXTEND_OP(MODE) ZERO_EXTEND
/* Nonzero if access to memory by bytes is slow and undesirable. */
#define SLOW_BYTE_ACCESS 1
......
gcc/config/romp/romp.h
......@@ -1186,9 +1186,15 @@ struct rt_cargs {int gregs, fregs; };
is undesirable. */
#define SLOW_BYTE_ACCESS 1
/* Define if normal loads of shorter-than-word items from memory clears
the rest of the bigs in the register. */
#define BYTE_LOADS_ZERO_EXTEND
/* Define if operations between registers always perform the operation
on the full register even if a narrower mode is specified. */
#define WORD_REGISTER_OPERATIONS
/* Define if loading in MODE, an integral mode narrower than BITS_PER_WORD
will either zero-extend or sign-extend. The value of this macro should
be the code that says which one of the two operations is implicitly
done, NIL if none. */
#define LOAD_EXTEND_OP(MODE) ZERO_EXTEND
/* This is BSD, so it wants DBX format. */
#define DBX_DEBUGGING_INFO
......
gcc/config/rs6000/rs6000.h
......@@ -1288,9 +1288,15 @@ struct rs6000_args {int words, fregno, nargs_prototype; };
is undesirable. */
#define SLOW_BYTE_ACCESS 1
/* Define if normal loads of shorter-than-word items from memory clears
the rest of the bigs in the register. */
#define BYTE_LOADS_ZERO_EXTEND
/* Define if operations between registers always perform the operation
on the full register even if a narrower mode is specified. */
#define WORD_REGISTER_OPERATIONS
/* Define if loading in MODE, an integral mode narrower than BITS_PER_WORD
will either zero-extend or sign-extend. The value of this macro should
be the code that says which one of the two operations is implicitly
done, NIL if none. */
#define LOAD_EXTEND_OP(MODE) ZERO_EXTEND
/* Define if loading short immediate values into registers sign extends. */
#define SHORT_IMMEDIATES_SIGN_EXTEND
......
gcc/config/sh/sh.h
......@@ -902,9 +902,15 @@ extern int current_function_anonymous_args;
in one reasonably fast instruction. */
#define MOVE_MAX 4
/* Define if normal loads of shorter-than-word items from sign extends
the rest of the bigs in the register. */
#define BYTE_LOADS_SIGN_EXTEND 1
/* Define if operations between registers always perform the operation
on the full register even if a narrower mode is specified. */
#define WORD_REGISTER_OPERATIONS
/* Define if loading in MODE, an integral mode narrower than BITS_PER_WORD
will either zero-extend or sign-extend. The value of this macro should
be the code that says which one of the two operations is implicitly
done, NIL if none. */
#define LOAD_EXTEND_OP(MODE) SIGN_EXTEND
/* Define this if zero-extension is slow (more than one real instruction).
On the SH, it's only one instruction */
......
gcc/config/sparc/sparc.h
......@@ -1348,9 +1348,15 @@ extern struct rtx_def *legitimize_pic_address ();
gen_rtx (MEM, SImode, gen_rtx (SYMBOL_REF, Pmode, "errno"))
#endif /* 0 */
/* Define if normal loads of shorter-than-word items from memory clears
the rest of the bigs in the register. */
#define BYTE_LOADS_ZERO_EXTEND
/* Define if operations between registers always perform the operation
on the full register even if a narrower mode is specified. */
#define WORD_REGISTER_OPERATIONS
/* Define if loading in MODE, an integral mode narrower than BITS_PER_WORD
will either zero-extend or sign-extend. The value of this macro should
be the code that says which one of the two operations is implicitly
done, NIL if none. */
#define LOAD_EXTEND_OP(MODE) ZERO_EXTEND
/* Nonzero if access to memory by bytes is slow and undesirable.
For RISC chips, it means that access to memory by bytes is no
......
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