i386.c (x86_partial_flag_reg_stall): New.

2006-09-07  H.J. Lu  <hongjiu.lu@intel.com>

	* config/i386/i386.c (x86_partial_flag_reg_stall): New.

	* config/i386/i386.h (x86_partial_flag_reg_stall): New.
	(TARGET_PARTIAL_FLAG_REG_STALL): New.

	* config/i386/i386.md (*ashldi3_cmp_rex64): Disabled for
	TARGET_PARTIAL_FLAG_REG_STALL.
	(*ashldi3_cconly_rex64): Likewise.
	(*ashlsi3_cmp): Likewise.
	(*ashlsi3_cconly): Likewise.
	(*ashlsi3_cmp_zext): Likewise.
	(*ashlhi3_cmp): Likewise.
	(*ashlhi3_cconly): Likewise.
	(*ashlqi3_cmp): Likewise.
	(*ashlqi3_cconly): Likewise.
	(*ashrdi3_cmp_rex64): Likewise.
	(*ashrdi3_cconly_rex64): Likewise.
	(*ashrsi3_cmp): Likewise.
	(*ashrsi3_cconly): Likewise.
	(*ashrsi3_cmp_zext): Likewise.
	(*ashrhi3_cmp): Likewise.
	(*ashrhi3_cconly): Likewise.
	(*ashrqi3_cmp): Likewise.
	(*ashrqi3_cconly): Likewise.
	(*lshrdi3_cmp_rex64): Likewise.
	(*lshrdi3_cconly_rex64): Likewise.
	(*lshrsi3_cmp): Likewise.
	(*lshrsi3_cconly): Likewise.
	(*lshrsi3_cmp_zext): Likewise.
	(*lshrhi3_cmp): Likewise.
	(*lshrhi3_cconly): Likewise.
	(*lshrqi2_cmp): Likewise.
	(*lshrqi2_cconly): Likewise.

From-SVN: r116757

gcc/ChangeLog

+2006-09-07  H.J. Lu  <hongjiu.lu@intel.com>
+
+	* config/i386/i386.c (x86_partial_flag_reg_stall): New.
+
+	* config/i386/i386.h (x86_partial_flag_reg_stall): New.
+	(TARGET_PARTIAL_FLAG_REG_STALL): New.
+
+	* config/i386/i386.md (*ashldi3_cmp_rex64): Disabled for
+	TARGET_PARTIAL_FLAG_REG_STALL.
+	(*ashldi3_cconly_rex64): Likewise.
+	(*ashlsi3_cmp): Likewise.
+	(*ashlsi3_cconly): Likewise.
+	(*ashlsi3_cmp_zext): Likewise.
+	(*ashlhi3_cmp): Likewise.
+	(*ashlhi3_cconly): Likewise.
+	(*ashlqi3_cmp): Likewise.
+	(*ashlqi3_cconly): Likewise.
+	(*ashrdi3_cmp_rex64): Likewise.
+	(*ashrdi3_cconly_rex64): Likewise.
+	(*ashrsi3_cmp): Likewise.
+	(*ashrsi3_cconly): Likewise.
+	(*ashrsi3_cmp_zext): Likewise.
+	(*ashrhi3_cmp): Likewise.
+	(*ashrhi3_cconly): Likewise.
+	(*ashrqi3_cmp): Likewise.
+	(*ashrqi3_cconly): Likewise.
+	(*lshrdi3_cmp_rex64): Likewise.
+	(*lshrdi3_cconly_rex64): Likewise.
+	(*lshrsi3_cmp): Likewise.
+	(*lshrsi3_cconly): Likewise.
+	(*lshrsi3_cmp_zext): Likewise.
+	(*lshrhi3_cmp): Likewise.
+	(*lshrhi3_cconly): Likewise.
+	(*lshrqi2_cmp): Likewise.
+	(*lshrqi2_cconly): Likewise.
+
 2006-09-07 Uros Bizjak <uros@kss-loka.si>
 
 	PR target/28946

gcc/config/i386/i386.c

@@ -761,6 +761,7 @@ const int x86_use_sahf = m_PPRO | m_K6 | m_PENT4 | m_NOCONA | m_GENERIC32; /*m_G
    with partial reg. dependencies used by Athlon/P4 based chips, it is better
    to leave it off for generic32 for now.  */
 const int x86_partial_reg_stall = m_PPRO;
+const int x86_partial_flag_reg_stall = m_GENERIC;
 const int x86_use_himode_fiop = m_386 | m_486 | m_K6;
 const int x86_use_simode_fiop = ~(m_PPRO | m_ATHLON_K8 | m_PENT | m_GENERIC);
 const int x86_use_mov0 = m_K6;

gcc/config/i386/i386.h

@@ -164,6 +164,7 @@ extern const int x86_use_bt;
 extern const int x86_cmpxchg, x86_cmpxchg8b, x86_cmpxchg16b, x86_xadd;
 extern const int x86_use_incdec;
 extern const int x86_pad_returns;
+extern const int x86_partial_flag_reg_stall;
 extern int x86_prefetch_sse;
 
 #define TARGET_USE_LEAVE (x86_use_leave & TUNEMASK)
@@ -182,6 +183,7 @@ extern int x86_prefetch_sse;
 #define TARGET_USE_SAHF ((x86_use_sahf & TUNEMASK) && !TARGET_64BIT)
 #define TARGET_MOVX (x86_movx & TUNEMASK)
 #define TARGET_PARTIAL_REG_STALL (x86_partial_reg_stall & TUNEMASK)
+#define TARGET_PARTIAL_FLAG_REG_STALL (x86_partial_flag_reg_stall & TUNEMASK)
 #define TARGET_USE_HIMODE_FIOP (x86_use_himode_fiop & TUNEMASK)
 #define TARGET_USE_SIMODE_FIOP (x86_use_simode_fiop & TUNEMASK)
 #define TARGET_USE_MOV0 (x86_use_mov0 & TUNEMASK)