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Commit 99176a91 by Aldy Hernandez Committed by Aldy Hernandez
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rs6000.md (fix_truncdfsi2): Handle e500 doubles. 

	* config/rs6000/rs6000.md (fix_truncdfsi2): Handle e500
	doubles.
	(floatunssidf2): Same.
	(floatsidf2): Same.
	("extendsfdf2"): New expander.
	(*extendsfdf2_fpr): Rename.
	(*truncdfsf2_fpr): Same.
	(*negdf2_fpr): Same.
	(*absdf2_fpr): Same.
	(*nabsdf2_fpr): Same.
	(*adddf3_fpr): Same.
	(*subdf3_fpr): Same.
	(*muldf3_fpr): Same.
	(*divdf3_fpr): Same.

	* config/rs6000/spe.md ("spe_extendsfdf2"): Remove FIXME comment.
	("spe_fix_truncdfsi2"): Same.
	(spe_floatunssidf2): Same.
	(spe_floatsidf2): Same.

From-SVN: r90379
parent df2ae6e2
Showing with 55 additions and 15 deletions
gcc/ChangeLog
2004-10-22 Aldy Hernandez <aldyh@redhat.com>
* config/rs6000/rs6000.md (fix_truncdfsi2): Handle e500
doubles.
(floatunssidf2): Same.
(floatsidf2): Same.
("extendsfdf2"): New expander.
(*extendsfdf2_fpr): Rename.
(*truncdfsf2_fpr): Same.
(*negdf2_fpr): Same.
(*absdf2_fpr): Same.
(*nabsdf2_fpr): Same.
(*adddf3_fpr): Same.
(*subdf3_fpr): Same.
(*muldf3_fpr): Same.
(*divdf3_fpr): Same.
* config/rs6000/spe.md ("spe_extendsfdf2"): Remove FIXME comment.
("spe_fix_truncdfsi2"): Same.
(spe_floatunssidf2): Same.
(spe_floatsidf2): Same.
2004-11-09 Joseph S. Myers <joseph@codesourcery.com> 2004-11-09 Joseph S. Myers <joseph@codesourcery.com>
PR c/18322 PR c/18322
......
gcc/config/rs6000/rs6000.md
...@@ -4458,7 +4458,13 @@ ...@@ -4458,7 +4458,13 @@
;; this case, we just lose precision that we would have otherwise gotten but ;; this case, we just lose precision that we would have otherwise gotten but
;; is not guaranteed. Perhaps this should be tightened up at some point. ;; is not guaranteed. Perhaps this should be tightened up at some point.
(define_insn_and_split "extendsfdf2" (define_expand "extendsfdf2"
[(set (match_operand:DF 0 "gpc_reg_operand" "")
(float_extend:DF (match_operand:SF 1 "gpc_reg_operand" "")))]
"TARGET_HARD_FLOAT && (TARGET_FPRS || TARGET_E500_DOUBLE)"
"")
(define_insn_and_split "*extendsfdf2_fpr"
[(set (match_operand:DF 0 "gpc_reg_operand" "=f,?f") [(set (match_operand:DF 0 "gpc_reg_operand" "=f,?f")
(float_extend:DF (match_operand:SF 1 "gpc_reg_operand" "0,f")))] (float_extend:DF (match_operand:SF 1 "gpc_reg_operand" "0,f")))]
"TARGET_HARD_FLOAT && TARGET_FPRS" "TARGET_HARD_FLOAT && TARGET_FPRS"
...@@ -4479,7 +4485,7 @@ ...@@ -4479,7 +4485,7 @@
"TARGET_HARD_FLOAT && (TARGET_FPRS || TARGET_E500_DOUBLE)" "TARGET_HARD_FLOAT && (TARGET_FPRS || TARGET_E500_DOUBLE)"
"") "")
(define_insn "fpr_truncdfsf2" (define_insn "*truncdfsf2_fpr"
[(set (match_operand:SF 0 "gpc_reg_operand" "=f") [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
(float_truncate:SF (match_operand:DF 1 "gpc_reg_operand" "f")))] (float_truncate:SF (match_operand:DF 1 "gpc_reg_operand" "f")))]
"TARGET_HARD_FLOAT && TARGET_FPRS" "TARGET_HARD_FLOAT && TARGET_FPRS"
...@@ -4875,7 +4881,7 @@ ...@@ -4875,7 +4881,7 @@
"TARGET_HARD_FLOAT && (TARGET_FPRS || TARGET_E500_DOUBLE)" "TARGET_HARD_FLOAT && (TARGET_FPRS || TARGET_E500_DOUBLE)"
"") "")
(define_insn "fpr_negdf2" (define_insn "*negdf2_fpr"
[(set (match_operand:DF 0 "gpc_reg_operand" "=f") [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
(neg:DF (match_operand:DF 1 "gpc_reg_operand" "f")))] (neg:DF (match_operand:DF 1 "gpc_reg_operand" "f")))]
"TARGET_HARD_FLOAT && TARGET_FPRS" "TARGET_HARD_FLOAT && TARGET_FPRS"
...@@ -4888,14 +4894,14 @@ ...@@ -4888,14 +4894,14 @@
"TARGET_HARD_FLOAT && (TARGET_FPRS || TARGET_E500_DOUBLE)" "TARGET_HARD_FLOAT && (TARGET_FPRS || TARGET_E500_DOUBLE)"
"") "")
(define_insn "fpr_absdf2" (define_insn "*absdf2_fpr"
[(set (match_operand:DF 0 "gpc_reg_operand" "=f") [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
(abs:DF (match_operand:DF 1 "gpc_reg_operand" "f")))] (abs:DF (match_operand:DF 1 "gpc_reg_operand" "f")))]
"TARGET_HARD_FLOAT && TARGET_FPRS" "TARGET_HARD_FLOAT && TARGET_FPRS"
"fabs %0,%1" "fabs %0,%1"
[(set_attr "type" "fp")]) [(set_attr "type" "fp")])
(define_insn "fpr_nabsdf2" (define_insn "*nabsdf2_fpr"
[(set (match_operand:DF 0 "gpc_reg_operand" "=f") [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
(neg:DF (abs:DF (match_operand:DF 1 "gpc_reg_operand" "f"))))] (neg:DF (abs:DF (match_operand:DF 1 "gpc_reg_operand" "f"))))]
"TARGET_HARD_FLOAT && TARGET_FPRS" "TARGET_HARD_FLOAT && TARGET_FPRS"
...@@ -4909,7 +4915,7 @@ ...@@ -4909,7 +4915,7 @@
"TARGET_HARD_FLOAT && (TARGET_FPRS || TARGET_E500_DOUBLE)" "TARGET_HARD_FLOAT && (TARGET_FPRS || TARGET_E500_DOUBLE)"
"") "")
(define_insn "fpr_adddf3" (define_insn "*adddf3_fpr"
[(set (match_operand:DF 0 "gpc_reg_operand" "=f") [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
(plus:DF (match_operand:DF 1 "gpc_reg_operand" "%f") (plus:DF (match_operand:DF 1 "gpc_reg_operand" "%f")
(match_operand:DF 2 "gpc_reg_operand" "f")))] (match_operand:DF 2 "gpc_reg_operand" "f")))]
...@@ -4924,7 +4930,7 @@ ...@@ -4924,7 +4930,7 @@
"TARGET_HARD_FLOAT && (TARGET_FPRS || TARGET_E500_DOUBLE)" "TARGET_HARD_FLOAT && (TARGET_FPRS || TARGET_E500_DOUBLE)"
"") "")
(define_insn "fpr_subdf3" (define_insn "*subdf3_fpr"
[(set (match_operand:DF 0 "gpc_reg_operand" "=f") [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
(minus:DF (match_operand:DF 1 "gpc_reg_operand" "f") (minus:DF (match_operand:DF 1 "gpc_reg_operand" "f")
(match_operand:DF 2 "gpc_reg_operand" "f")))] (match_operand:DF 2 "gpc_reg_operand" "f")))]
...@@ -4939,7 +4945,7 @@ ...@@ -4939,7 +4945,7 @@
"TARGET_HARD_FLOAT && (TARGET_FPRS || TARGET_E500_DOUBLE)" "TARGET_HARD_FLOAT && (TARGET_FPRS || TARGET_E500_DOUBLE)"
"") "")
(define_insn "fpr_muldf3" (define_insn "*muldf3_fpr"
[(set (match_operand:DF 0 "gpc_reg_operand" "=f") [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
(mult:DF (match_operand:DF 1 "gpc_reg_operand" "%f") (mult:DF (match_operand:DF 1 "gpc_reg_operand" "%f")
(match_operand:DF 2 "gpc_reg_operand" "f")))] (match_operand:DF 2 "gpc_reg_operand" "f")))]
...@@ -4954,7 +4960,7 @@ ...@@ -4954,7 +4960,7 @@
"TARGET_HARD_FLOAT && (TARGET_FPRS || TARGET_E500_DOUBLE)" "TARGET_HARD_FLOAT && (TARGET_FPRS || TARGET_E500_DOUBLE)"
"") "")
(define_insn "fpr_divdf3" (define_insn "*divdf3_fpr"
[(set (match_operand:DF 0 "gpc_reg_operand" "=f") [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
(div:DF (match_operand:DF 1 "gpc_reg_operand" "f") (div:DF (match_operand:DF 1 "gpc_reg_operand" "f")
(match_operand:DF 2 "gpc_reg_operand" "f")))] (match_operand:DF 2 "gpc_reg_operand" "f")))]
...@@ -5125,6 +5131,11 @@ ...@@ -5125,6 +5131,11 @@
"TARGET_HARD_FLOAT && TARGET_FPRS" "TARGET_HARD_FLOAT && TARGET_FPRS"
" "
{ {
if (TARGET_E500_DOUBLE)
{
emit_insn (gen_spe_floatsidf2 (operands[0], operands[1]));
DONE;
}
if (TARGET_POWERPC64) if (TARGET_POWERPC64)
{ {
rtx mem = assign_stack_temp (DImode, GET_MODE_SIZE (DImode), 0); rtx mem = assign_stack_temp (DImode, GET_MODE_SIZE (DImode), 0);
...@@ -5204,9 +5215,14 @@ ...@@ -5204,9 +5215,14 @@
(use (match_dup 3)) (use (match_dup 3))
(clobber (match_dup 4)) (clobber (match_dup 4))
(clobber (match_dup 5))])] (clobber (match_dup 5))])]
"TARGET_HARD_FLOAT && TARGET_FPRS" "TARGET_HARD_FLOAT && (TARGET_FPRS || TARGET_E500_DOUBLE)"
" "
{ {
if (TARGET_E500_DOUBLE)
{
emit_insn (gen_spe_floatunssidf2 (operands[0], operands[1]));
DONE;
}
if (TARGET_POWERPC64) if (TARGET_POWERPC64)
{ {
rtx mem = assign_stack_temp (DImode, GET_MODE_SIZE (DImode), 0); rtx mem = assign_stack_temp (DImode, GET_MODE_SIZE (DImode), 0);
...@@ -5273,9 +5289,15 @@ ...@@ -5273,9 +5289,15 @@
(fix:SI (match_operand:DF 1 "gpc_reg_operand" ""))) (fix:SI (match_operand:DF 1 "gpc_reg_operand" "")))
(clobber (match_dup 2)) (clobber (match_dup 2))
(clobber (match_dup 3))])] (clobber (match_dup 3))])]
"(TARGET_POWER2 || TARGET_POWERPC) && TARGET_HARD_FLOAT && TARGET_FPRS" "(TARGET_POWER2 || TARGET_POWERPC)
&& TARGET_HARD_FLOAT && (TARGET_FPRS || TARGET_E500_DOUBLE)"
" "
{ {
if (TARGET_E500_DOUBLE)
{
emit_insn (gen_spe_fix_truncdfsi2 (operands[0], operands[1]));
DONE;
}
operands[2] = gen_reg_rtx (DImode); operands[2] = gen_reg_rtx (DImode);
operands[3] = assign_stack_temp (DImode, GET_MODE_SIZE (DImode), 0); operands[3] = assign_stack_temp (DImode, GET_MODE_SIZE (DImode), 0);
}") }")
......
gcc/config/rs6000/spe.md
...@@ -93,7 +93,6 @@ ...@@ -93,7 +93,6 @@
"efdctuiz %0,%1" "efdctuiz %0,%1"
[(set_attr "type" "fp")]) [(set_attr "type" "fp")])
;; FIXME: fix expander.
(define_insn "spe_extendsfdf2" (define_insn "spe_extendsfdf2"
[(set (match_operand:DF 0 "gpc_reg_operand" "=r") [(set (match_operand:DF 0 "gpc_reg_operand" "=r")
(float_extend:DF (match_operand:SF 1 "gpc_reg_operand" "r")))] (float_extend:DF (match_operand:SF 1 "gpc_reg_operand" "r")))]
...@@ -115,7 +114,6 @@ ...@@ -115,7 +114,6 @@
"efsctsiz %0,%1" "efsctsiz %0,%1"
[(set_attr "type" "fp")]) [(set_attr "type" "fp")])
;; FIXME: fix expander.
(define_insn "spe_fix_truncdfsi2" (define_insn "spe_fix_truncdfsi2"
[(set (match_operand:SI 0 "gpc_reg_operand" "=r") [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
(fix:SI (match_operand:DF 1 "gpc_reg_operand" "r")))] (fix:SI (match_operand:DF 1 "gpc_reg_operand" "r")))]
...@@ -130,7 +128,6 @@ ...@@ -130,7 +128,6 @@
"efscfui %0,%1" "efscfui %0,%1"
[(set_attr "type" "fp")]) [(set_attr "type" "fp")])
;; FIXME: fix expander.
(define_insn "spe_floatunssidf2" (define_insn "spe_floatunssidf2"
[(set (match_operand:DF 0 "gpc_reg_operand" "=r") [(set (match_operand:DF 0 "gpc_reg_operand" "=r")
(unsigned_float:DF (match_operand:SI 1 "gpc_reg_operand" "r")))] (unsigned_float:DF (match_operand:SI 1 "gpc_reg_operand" "r")))]
...@@ -145,7 +142,6 @@ ...@@ -145,7 +142,6 @@
"efscfsi %0,%1" "efscfsi %0,%1"
[(set_attr "type" "fp")]) [(set_attr "type" "fp")])
;; FIXME: fix expander.
(define_insn "spe_floatsidf2" (define_insn "spe_floatsidf2"
[(set (match_operand:DF 0 "gpc_reg_operand" "=r") [(set (match_operand:DF 0 "gpc_reg_operand" "=r")
(float:DF (match_operand:SI 1 "gpc_reg_operand" "r")))] (float:DF (match_operand:SI 1 "gpc_reg_operand" "r")))]
......
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