*** empty log message ***

From-SVN: r372

gcc/config/m68k/m68k.md

@@ -1828,6 +1828,12 @@
   return \"add%.w %2,%0\";
 }")
 
+;; These insns must use MATCH_DUP instead of the more expected
+;; use of a matching constraint because the "output" here is also
+;; an input, so you can't use the matching constraint.  That also means
+;; that you can't use the "%", so you need patterns with the matched
+;; operand in both positions.
+
 (define_insn ""
   [(set (strict_low_part (match_operand:HI 0 "general_operand" "+m,d"))
 	(plus:HI (match_dup 0)
@@ -1835,6 +1841,13 @@
   ""
   "add%.w %1,%0")
 
+(define_insn ""
+  [(set (strict_low_part (match_operand:HI 0 "general_operand" "+m,d"))
+	(plus:HI (match_operand:HI 1 "general_operand" "dn,rmn")
+		 (match_dup 0)))]
+  ""
+  "add%.w %1,%0")
+
 (define_insn "addqi3"
   [(set (match_operand:QI 0 "general_operand" "=m,d")
 	(plus:QI (match_operand:QI 1 "general_operand" "%0,0")
@@ -1868,6 +1881,13 @@
   ""
   "add%.b %1,%0")
 
+(define_insn ""
+  [(set (strict_low_part (match_operand:QI 0 "general_operand" "+m,d"))
+	(plus:QI (match_operand:QI 1 "general_operand" "dn,dmn")
+		 (match_dup 0)))]
+  ""
+  "add%.b %1,%0")
+
 (define_expand "adddf3"
   [(set (match_operand:DF 0 "general_operand" "")
 	(plus:DF (match_operand:DF 1 "general_operand" "")
@@ -2721,6 +2741,20 @@
   ""
   "and%.w %2,%0")
 
+(define_insn ""
+  [(set (strict_low_part (match_operand:HI 0 "general_operand" "+m,d"))
+	(and:HI (match_dup 0)
+		(match_operand:HI 1 "general_operand" "dn,dmn")))]
+  ""
+  "and%.w %1,%0")
+
+(define_insn ""
+  [(set (strict_low_part (match_operand:HI 0 "general_operand" "+m,d"))
+	(and:HI (match_operand:HI 1 "general_operand" "dn,dmn")
+		(match_dup 0)))]
+  ""
+  "and%.w %1,%0")
+
 (define_insn "andqi3"
   [(set (match_operand:QI 0 "general_operand" "=m,d")
 	(and:QI (match_operand:QI 1 "general_operand" "%0,0")
@@ -2728,6 +2762,19 @@
   ""
   "and%.b %2,%0")
 
+(define_insn ""
+  [(set (strict_low_part (match_operand:QI 0 "general_operand" "+m,d"))
+	(and:QI (match_dup 0)
+		(match_operand:QI 1 "general_operand" "dn,dmn")))]
+  ""
+  "and%.b %1,%0")
+
+(define_insn ""
+  [(set (strict_low_part (match_operand:QI 0 "general_operand" "+m,d"))
+	(and:QI (match_operand:QI 1 "general_operand" "dn,dmn")
+		(match_dup 0)))]
+  ""
+  "and%.b %1,%0")
 
 ;; inclusive-or instructions
 
@@ -2776,12 +2823,40 @@
   ""
   "or%.w %2,%0")
 
+(define_insn ""
+  [(set (strict_low_part (match_operand:HI 0 "general_operand" "+m,d"))
+	(ior:HI (match_dup 0)
+		(match_operand:HI 1 "general_operand" "dn,dmn")))]
+  ""
+  "or%.w %1,%0")
+
+(define_insn ""
+  [(set (strict_low_part (match_operand:HI 0 "general_operand" "+m,d"))
+	(ior:HI (match_operand:HI 1 "general_operand" "dn,dmn")
+		(match_dup 0)))]
+  ""
+  "or%.w %1,%0")
+
 (define_insn "iorqi3"
   [(set (match_operand:QI 0 "general_operand" "=m,d")
 	(ior:QI (match_operand:QI 1 "general_operand" "%0,0")
 		(match_operand:QI 2 "general_operand" "dn,dmn")))]
   ""
   "or%.b %2,%0")
+
+(define_insn ""
+  [(set (strict_low_part (match_operand:QI 0 "general_operand" "+m,d"))
+	(ior:QI (match_dup 0)
+		(match_operand:QI 1 "general_operand" "dn,dmn")))]
+  ""
+  "or%.b %1,%0")
+
+(define_insn ""
+  [(set (strict_low_part (match_operand:QI 0 "general_operand" "+m,d"))
+	(ior:QI (match_operand:QI 1 "general_operand" "dn,dmn")
+		(match_dup 0)))]
+  ""
+  "or%.b %1,%0")
 
 ;; xor instructions
 
@@ -2812,12 +2887,41 @@
   ""
   "eor%.w %2,%0")
 
+(define_insn ""
+  [(set (strict_low_part (match_operand:HI 0 "general_operand" "+dm"))
+	(xor:HI (match_dup 0)
+		(match_operand:HI 1 "general_operand" "dn")))]
+  ""
+  "eor%.w %1,%0")
+
+
+(define_insn ""
+  [(set (strict_low_part (match_operand:HI 0 "general_operand" "+dm"))
+	(xor:HI (match_operand:HI 1 "general_operand" "dn")
+		(match_dup 0)))]
+  ""
+  "eor%.w %1,%0")
+
 (define_insn "xorqi3"
   [(set (match_operand:QI 0 "general_operand" "=dm")
 	(xor:QI (match_operand:QI 1 "general_operand" "%0")
 		(match_operand:QI 2 "general_operand" "dn")))]
   ""
   "eor%.b %2,%0")
+
+(define_insn ""
+  [(set (strict_low_part (match_operand:QI 0 "general_operand" "+dm"))
+	(xor:QI (match_dup 0)
+		(match_operand:QI 1 "general_operand" "dn")))]
+  ""
+  "eor%.b %1,%0")
+
+(define_insn ""
+  [(set (strict_low_part (match_operand:QI 0 "general_operand" "+dm"))
+	(xor:QI (match_operand:QI 1 "general_operand" "dn")
+		(match_dup 0)))]
+  ""
+  "eor%.b %1,%0")
 
 ;; negation instructions
 
@@ -2833,12 +2937,24 @@
   ""
   "neg%.w %0")
 
+(define_insn ""
+  [(set (strict_low_part (match_operand:HI 0 "general_operand" "+dm"))
+	(neg:HI (match_dup 0)))]
+  ""
+  "neg%.w %0")
+
 (define_insn "negqi2"
   [(set (match_operand:QI 0 "general_operand" "=dm")
 	(neg:QI (match_operand:QI 1 "general_operand" "0")))]
   ""
   "neg%.b %0")
 
+(define_insn ""
+  [(set (strict_low_part (match_operand:QI 0 "general_operand" "+dm"))
+	(neg:QI (match_dup 0)))]
+  ""
+  "neg%.b %0")
+
 (define_expand "negsf2"
   [(set (match_operand:SF 0 "general_operand" "")
 	(neg:SF (match_operand:SF 1 "general_operand" "")))]
@@ -2957,11 +3073,23 @@
   ""
   "not%.w %0")
 
+(define_insn ""
+  [(set (strict_low_part (match_operand:HI 0 "general_operand" "+dm"))
+	(not:HI (match_dup 0)))]
+  ""
+  "not%.w %0")
+
 (define_insn "one_cmplqi2"
   [(set (match_operand:QI 0 "general_operand" "=dm")
 	(not:QI (match_operand:QI 1 "general_operand" "0")))]
   ""
   "not%.b %0")
+
+(define_insn ""
+  [(set (strict_low_part (match_operand:QI 0 "general_operand" "+dm"))
+	(not:QI (match_dup 0)))]
+  ""
+  "not%.b %0")
 
 ;; arithmetic shift instructions
 ;; We don't need the shift memory by 1 bit instruction
@@ -3004,6 +3132,13 @@
   ""
   "asl%.w %2,%0")
 
+(define_insn ""
+  [(set (strict_low_part (match_operand:HI 0 "register_operand" "+d"))
+	(ashift:HI (match_dup 0)
+		   (match_operand:HI 1 "general_operand" "dI")))]
+  ""
+  "asl%.w %1,%0")
+
 (define_insn "ashlqi3"
   [(set (match_operand:QI 0 "register_operand" "=d")
 	(ashift:QI (match_operand:QI 1 "register_operand" "0")
@@ -3011,6 +3146,13 @@
   ""
   "asl%.b %2,%0")
 
+(define_insn ""
+  [(set (strict_low_part (match_operand:QI 0 "register_operand" "+d"))
+	(ashift:QI (match_dup 0)
+		   (match_operand:QI 1 "general_operand" "dI")))]
+  ""
+  "asl%.b %1,%0")
+
 ;; On the 68000, this makes faster code in a special case.
 
 (define_insn ""
@@ -3045,12 +3187,26 @@
   ""
   "asr%.w %2,%0")
 
+(define_insn ""
+  [(set (strict_low_part (match_operand:HI 0 "register_operand" "+d"))
+	(ashiftrt:HI (match_dup 0)
+		     (match_operand:HI 1 "general_operand" "dI")))]
+  ""
+  "asr%.w %1,%0")
+
 (define_insn "ashrqi3"
   [(set (match_operand:QI 0 "register_operand" "=d")
 	(ashiftrt:QI (match_operand:QI 1 "register_operand" "0")
 		     (match_operand:QI 2 "general_operand" "dI")))]
   ""
   "asr%.b %2,%0")
+
+(define_insn ""
+  [(set (strict_low_part (match_operand:QI 0 "register_operand" "+d"))
+	(ashiftrt:QI (match_dup 0)
+		     (match_operand:QI 1 "general_operand" "dI")))]
+  ""
+  "asr%.b %1,%0")
 
 ;; logical shift instructions
 
@@ -3092,6 +3248,13 @@
   ""
   "lsl%.w %2,%0")
 
+(define_insn ""
+  [(set (strict_low_part (match_operand:HI 0 "register_operand" "+d"))
+	(lshift:HI (match_dup 0)
+		   (match_operand:HI 1 "general_operand" "dI")))]
+  ""
+  "lsl%.w %1,%0")
+
 (define_insn "lshlqi3"
   [(set (match_operand:QI 0 "register_operand" "=d")
 	(lshift:QI (match_operand:QI 1 "register_operand" "0")
@@ -3099,6 +3262,13 @@
   ""
   "lsl%.b %2,%0")
 
+(define_insn ""
+  [(set (strict_low_part (match_operand:QI 0 "register_operand" "+d"))
+	(lshift:QI (match_dup 0)
+		   (match_operand:QI 1 "general_operand" "dI")))]
+  ""
+  "lsl%.b %1,%0")
+
 ;; On the 68000, this makes faster code in a special case.
 
 (define_insn ""
@@ -3137,12 +3307,26 @@
   ""
   "lsr%.w %2,%0")
 
+(define_insn ""
+  [(set (strict_low_part (match_operand:HI 0 "register_operand" "+d"))
+	(lshiftrt:HI (match_dup 0)
+		     (match_operand:HI 1 "general_operand" "dI")))]
+  ""
+  "lsr%.w %1,%0")
+
 (define_insn "lshrqi3"
   [(set (match_operand:QI 0 "register_operand" "=d")
 	(lshiftrt:QI (match_operand:QI 1 "register_operand" "0")
 		     (match_operand:QI 2 "general_operand" "dI")))]
   ""
   "lsr%.b %2,%0")
+
+(define_insn ""
+  [(set (strict_low_part (match_operand:QI 0 "register_operand" "+d"))
+	(lshiftrt:QI (match_dup 0)
+		     (match_operand:QI 1 "general_operand" "dI")))]
+  ""
+  "lsr%.b %1,%0")
 
 ;; rotate instructions
 
@@ -3160,6 +3344,14 @@
   ""
   "rol%.w %2,%0")
 
+
+(define_insn ""
+  [(set (strict_low_part (match_operand:HI 0 "register_operand" "+d"))
+	(rotate:HI (match_dup 0)
+		   (match_operand:HI 1 "general_operand" "dI")))]
+  ""
+  "rol%.w %1,%0")
+
 (define_insn "rotlqi3"
   [(set (match_operand:QI 0 "register_operand" "=d")
 	(rotate:QI (match_operand:QI 1 "register_operand" "0")
@@ -3167,6 +3359,13 @@
   ""
   "rol%.b %2,%0")
 
+(define_insn ""
+  [(set (strict_low_part (match_operand:QI 0 "register_operand" "+d"))
+	(rotate:QI (match_dup 0)
+		   (match_operand:QI 1 "general_operand" "dI")))]
+  ""
+  "rol%.b %1,%0")
+
 (define_insn "rotrsi3"
   [(set (match_operand:SI 0 "register_operand" "=d")
 	(rotatert:SI (match_operand:SI 1 "register_operand" "0")
@@ -3181,12 +3380,26 @@
   ""
   "ror%.w %2,%0")
 
+(define_insn ""
+  [(set (strict_low_part (match_operand:HI 0 "register_operand" "+d"))
+	(rotatert:HI (match_dup 0)
+		     (match_operand:HI 1 "general_operand" "dI")))]
+  ""
+  "ror%.w %1,%0")
+
 (define_insn "rotrqi3"
   [(set (match_operand:QI 0 "register_operand" "=d")
 	(rotatert:QI (match_operand:QI 1 "register_operand" "0")
 		     (match_operand:QI 2 "general_operand" "dI")))]
   ""
   "ror%.b %2,%0")
+
+(define_insn ""
+  [(set (strict_low_part (match_operand:QI 0 "register_operand" "+d"))
+	(rotatert:QI (match_dup 0)
+		     (match_operand:QI 1 "general_operand" "dI")))]
+  ""
+  "ror%.b %1,%0")
 
 ;; Special cases of bit-field insns which we should
 ;; recognize in preference to the general case.