Skip to content

R
riscv-gcc-1
Commit 987a3082 by Uros Bizjak
Options

i386.md (@cmp<mode>_1): Rename from cmp<mode>_1. 

	* config/i386/i386.md (@cmp<mode>_1): Rename from cmp<mode>_1.
	(@add<mode>3_carry): Rename from add<mode>3_carry.
	(@sub<mode>3_carry_ccc): Rename from sub<mode>3_carry_ccc.
	(@sub<mode>3_carry_ccgz): Rename form sub<mode>3_carry_ccgz.
	(@copysign<mode>3_const): Rename from copysign<mode>3_const.
	(@copysign<mode>3_var): Rename from copysign<mode>3_var.
	(@xorsign<mode>3_1): Rename from xorsign<mode>3_1.
	(@x86_shift<mode>_adj_1): Rename from x86_shift<mode>_adj_1.
	(@x86_shift<mode>_adj_2): Rename from x86_shift<mode>_adj_2.
	(@x86_shift<mode>_adj_3): Rename from x86_shift<mode>_adj_3.
	(cmpstrnsi): Use gen_cmp_1.
	(lwp_slwpcb): Use gen_lwp_slwpcb_1.
	(@lwp_slwpcb<mode>_1): Rename from lwp_slwpcb<mode>_1.
	(@umonitor_<mode>): Rename from umonitor_<mode>.
	* config/i386/i386-expand.c (ix86_expand_copysign):
	Use gen_copysign3_const and gen_copysign3_var.
	(ix86_expand_xorsign): Use gen_xorsign3_1.
	(ix86_expand_branch): Use gen_sub3_carry_ccc,
	gen_sub3_carry_ccgz and gen_cmp1.
	(ix86_expand_int_addcc): Use gen_sub3_carry and gen_add3_carry.
	(ix86_split_ashl): Use gen_x86_shift_adj_1 and gen_x86_shift_adj_2.
	(ix86_split_ashr): Use gen_x86_shift_adj_1 and gen_x86_shift_adj_3.
	(ix86_split_lshr): Ditto.
	(ix86_expand_builtin) <case IX86_BUILTIN_UMONITOR>: Use gen_umonitor.

From-SVN: r272432
parent d0aa42d2
Showing with 88 additions and 165 deletions
gcc/ChangeLog
2019-06-18 Uroš Bizjak <ubizjak@gmail.com>
* config/i386/i386.md (@cmp<mode>_1): Rename from cmp<mode>_1.
(@add<mode>3_carry): Rename from add<mode>3_carry.
(@sub<mode>3_carry_ccc): Rename from sub<mode>3_carry_ccc.
(@sub<mode>3_carry_ccgz): Rename form sub<mode>3_carry_ccgz.
(@copysign<mode>3_const): Rename from copysign<mode>3_const.
(@copysign<mode>3_var): Rename from copysign<mode>3_var.
(@xorsign<mode>3_1): Rename from xorsign<mode>3_1.
(@x86_shift<mode>_adj_1): Rename from x86_shift<mode>_adj_1.
(@x86_shift<mode>_adj_2): Rename from x86_shift<mode>_adj_2.
(@x86_shift<mode>_adj_3): Rename from x86_shift<mode>_adj_3.
(cmpstrnsi): Use gen_cmp_1.
(lwp_slwpcb): Use gen_lwp_slwpcb_1.
(@lwp_slwpcb<mode>_1): Rename from lwp_slwpcb<mode>_1.
(@umonitor_<mode>): Rename from umonitor_<mode>.
* config/i386/i386-expand.c (ix86_expand_copysign):
Use gen_copysign3_const and gen_copysign3_var.
(ix86_expand_xorsign): Use gen_xorsign3_1.
(ix86_expand_branch): Use gen_sub3_carry_ccc,
gen_sub3_carry_ccgz and gen_cmp1.
(ix86_expand_int_addcc): Use gen_sub3_carry and gen_add3_carry.
(ix86_split_ashl): Use gen_x86_shift_adj_1 and gen_x86_shift_adj_2.
(ix86_split_ashr): Use gen_x86_shift_adj_1 and gen_x86_shift_adj_3.
(ix86_split_lshr): Ditto.
(ix86_expand_builtin) <case IX86_BUILTIN_UMONITOR>: Use gen_umonitor.
2019-06-18 Jason Merrill <jason@redhat.com>
* tree.c (build_constructor): Add MEM_STAT_DECL.
......@@ -55,7 +82,8 @@
* config/nvptx/nvptx-protos.h (gen_set_softstack_insn): Remove.
* config/nvptx/nvptx.c (gen_set_softstack_insn): Remove.
* config/nvptx/nvptx.md (define_insn "set_softstack_<mode>"): Rename to ...
* config/nvptx/nvptx.md (define_insn "set_softstack_<mode>"):
Rename to ...
(define_insn "@set_softstack_<mode>"): ... this.
(define_insn "omp_simt_enter_<mode>"): Rename to ...
(define_insn "@omp_simt_enter_<mode>"): ... this.
......
gcc/config/i386/i386.md
......@@ -1268,7 +1268,7 @@
DONE;
})
(define_expand "cmp<mode>_1"
(define_expand "@cmp<mode>_1"
[(set (reg:CC FLAGS_REG)
(compare:CC (match_operand:SWI48 0 "nonimmediate_operand")
(match_operand:SWI48 1 "<general_operand>")))])
......@@ -6503,7 +6503,7 @@
;; Add with carry and subtract with borrow
(define_insn "add<mode>3_carry"
(define_insn "@add<mode>3_carry"
[(set (match_operand:SWI 0 "nonimmediate_operand" "=<r>m,<r>")
(plus:SWI
(plus:SWI
......@@ -6665,7 +6665,7 @@
(set_attr "pent_pair" "pu")
(set_attr "mode" "SI")])
(define_insn "sub<mode>3_carry_ccc"
(define_insn "@sub<mode>3_carry_ccc"
[(set (reg:CCC FLAGS_REG)
(compare:CCC
(zero_extend:<DWI> (match_operand:DWIH 1 "register_operand" "0"))
......@@ -6699,7 +6699,7 @@
;; (compare (match_dup 1) (plus:DWIH (ltu:DWIH ...) (match_dup 2)))
;; result, the overflow flag likewise, but the overflow flag is also
;; set if the (plus:DWIH (ltu:DWIH ...) (match_dup 2)) overflows.
(define_insn "sub<mode>3_carry_ccgz"
(define_insn "@sub<mode>3_carry_ccgz"
[(set (reg:CCGZ FLAGS_REG)
(unspec:CCGZ [(match_operand:DWIH 1 "register_operand" "0")
(match_operand:DWIH 2 "x86_64_general_operand" "rme")
......@@ -9626,7 +9626,7 @@
|| (TARGET_SSE && (<MODE>mode == TFmode))"
"ix86_expand_copysign (operands); DONE;")
(define_insn_and_split "copysign<mode>3_const"
(define_insn_and_split "@copysign<mode>3_const"
[(set (match_operand:SSEMODEF 0 "register_operand" "=Yv")
(unspec:SSEMODEF
[(match_operand:<ssevecmodef> 1 "nonimm_or_0_operand" "YvmC")
......@@ -9640,7 +9640,7 @@
[(const_int 0)]
"ix86_split_copysign_const (operands); DONE;")
(define_insn "copysign<mode>3_var"
(define_insn "@copysign<mode>3_var"
[(set (match_operand:SSEMODEF 0 "register_operand" "=Yv,Yv,Yv,Yv,Yv")
(unspec:SSEMODEF
[(match_operand:SSEMODEF 2 "register_operand" "Yv,0,0,Yv,Yv")
......@@ -9677,7 +9677,7 @@
"SSE_FLOAT_MODE_P (<MODE>mode) && TARGET_SSE_MATH"
"ix86_expand_xorsign (operands); DONE;")
(define_insn_and_split "xorsign<mode>3_1"
(define_insn_and_split "@xorsign<mode>3_1"
[(set (match_operand:MODEF 0 "register_operand" "=Yv")
(unspec:MODEF
[(match_operand:MODEF 1 "register_operand" "Yv")
......@@ -9977,7 +9977,7 @@
(set_attr "amdfam10_decode" "vector")
(set_attr "bdver1_decode" "vector")])
(define_expand "x86_shift<mode>_adj_1"
(define_expand "@x86_shift<mode>_adj_1"
[(set (reg:CCZ FLAGS_REG)
(compare:CCZ (and:QI (match_operand:QI 2 "register_operand")
(match_dup 4))
......@@ -9993,7 +9993,7 @@
"TARGET_CMOVE"
"operands[4] = GEN_INT (GET_MODE_BITSIZE (<MODE>mode));")
(define_expand "x86_shift<mode>_adj_2"
(define_expand "@x86_shift<mode>_adj_2"
[(use (match_operand:SWI48 0 "register_operand"))
(use (match_operand:SWI48 1 "register_operand"))
(use (match_operand:QI 2 "register_operand"))]
......@@ -10773,7 +10773,7 @@
(set_attr "modrm" "0,1")
(set_attr "mode" "SI")])
(define_expand "x86_shift<mode>_adj_3"
(define_expand "@x86_shift<mode>_adj_3"
[(use (match_operand:SWI48 0 "register_operand"))
(use (match_operand:SWI48 1 "register_operand"))
(use (match_operand:QI 2 "register_operand"))]
......@@ -17059,12 +17059,7 @@
}
else
{
rtx (*gen_cmp) (rtx, rtx);
gen_cmp = (TARGET_64BIT
? gen_cmpdi_1 : gen_cmpsi_1);
emit_insn (gen_cmp (countreg, countreg));
emit_insn (gen_cmp_1 (Pmode, countreg, countreg));
emit_insn (gen_cmpstrnqi_1 (addr1, addr2, countreg, align,
operands[1], operands[2]));
}
......@@ -19819,7 +19814,7 @@
UNSPECV_LLWP_INTRINSIC)]
"TARGET_LWP")
(define_insn "*lwp_llwpcb<mode>1"
(define_insn "*lwp_llwpcb<mode>_1"
[(unspec_volatile [(match_operand:P 0 "register_operand" "r")]
UNSPECV_LLWP_INTRINSIC)]
"TARGET_LWP"
......@@ -19832,18 +19827,9 @@
[(set (match_operand 0 "register_operand")
(unspec_volatile [(const_int 0)] UNSPECV_SLWP_INTRINSIC))]
"TARGET_LWP"
{
rtx (*insn)(rtx);
insn = (Pmode == DImode
? gen_lwp_slwpcbdi
: gen_lwp_slwpcbsi);
emit_insn (insn (operands[0]));
DONE;
})
"emit_insn (gen_lwp_slwpcb_1 (Pmode, operands[0])); DONE;")
(define_insn "lwp_slwpcb<mode>"
(define_insn "@lwp_slwpcb<mode>_1"
[(set (match_operand:P 0 "register_operand" "=r")
(unspec_volatile:P [(const_int 0)] UNSPECV_SLWP_INTRINSIC))]
"TARGET_LWP"
......@@ -20305,7 +20291,7 @@
"umwait\t%0"
[(set_attr "length" "3")])
(define_insn "umonitor_<mode>"
(define_insn "@umonitor_<mode>"
[(unspec_volatile [(match_operand:P 0 "register_operand" "r")]
UNSPECV_UMONITOR)]
"TARGET_WAITPKG"
......
Markdown is supported
0% or
You are about to add 0 people to the discussion. Proceed with caution.
Finish editing this message first!
Please register or to comment