Commit 985e0d33 by James Greenhalgh Committed by James Greenhalgh

[ARM] [Trivial] Fix shortening of field name extend.

gcc/
	* config/arm/aarch-common-protos.h
	(alu_cost_table): Fix spelling of "extend".
	* config/arm/arm.c (arm_new_rtx_costs): Fix spelling of "extend".

From-SVN: r208683
parent ce2f49b3
2014-03-19 James Greenhalgh <james.greenhalgh@arm.com>
* config/arm/aarch-common-protos.h
(alu_cost_table): Fix spelling of "extend".
* config/arm/arm.c (arm_new_rtx_costs): Fix spelling of "extend".
2014-03-19 Richard Biener <rguenther@suse.de> 2014-03-19 Richard Biener <rguenther@suse.de>
PR middle-end/60553 PR middle-end/60553
......
...@@ -48,8 +48,8 @@ struct alu_cost_table ...@@ -48,8 +48,8 @@ struct alu_cost_table
const int arith_shift_reg; /* ... and when the shift is by a reg. */ const int arith_shift_reg; /* ... and when the shift is by a reg. */
const int log_shift; /* Additional when logic also shifts... */ const int log_shift; /* Additional when logic also shifts... */
const int log_shift_reg; /* ... and when the shift is by a reg. */ const int log_shift_reg; /* ... and when the shift is by a reg. */
const int extnd; /* Zero/sign extension. */ const int extend; /* Zero/sign extension. */
const int extnd_arith; /* Extend and arith. */ const int extend_arith; /* Extend and arith. */
const int bfi; /* Bit-field insert. */ const int bfi; /* Bit-field insert. */
const int bfx; /* Bit-field extraction. */ const int bfx; /* Bit-field extraction. */
const int clz; /* Count Leading Zeros. */ const int clz; /* Count Leading Zeros. */
......
...@@ -9594,7 +9594,7 @@ arm_new_rtx_costs (rtx x, enum rtx_code code, enum rtx_code outer_code, ...@@ -9594,7 +9594,7 @@ arm_new_rtx_costs (rtx x, enum rtx_code code, enum rtx_code outer_code,
{ {
/* UXTA[BH] or SXTA[BH]. */ /* UXTA[BH] or SXTA[BH]. */
if (speed_p) if (speed_p)
*cost += extra_cost->alu.extnd_arith; *cost += extra_cost->alu.extend_arith;
*cost += (rtx_cost (XEXP (XEXP (x, 0), 0), ZERO_EXTEND, 0, *cost += (rtx_cost (XEXP (XEXP (x, 0), 0), ZERO_EXTEND, 0,
speed_p) speed_p)
+ rtx_cost (XEXP (x, 1), PLUS, 0, speed_p)); + rtx_cost (XEXP (x, 1), PLUS, 0, speed_p));
...@@ -10311,7 +10311,7 @@ arm_new_rtx_costs (rtx x, enum rtx_code code, enum rtx_code outer_code, ...@@ -10311,7 +10311,7 @@ arm_new_rtx_costs (rtx x, enum rtx_code code, enum rtx_code outer_code,
*cost = COSTS_N_INSNS (1); *cost = COSTS_N_INSNS (1);
*cost += rtx_cost (XEXP (x, 0), code, 0, speed_p); *cost += rtx_cost (XEXP (x, 0), code, 0, speed_p);
if (speed_p) if (speed_p)
*cost += extra_cost->alu.extnd; *cost += extra_cost->alu.extend;
} }
else if (GET_MODE (XEXP (x, 0)) != SImode) else if (GET_MODE (XEXP (x, 0)) != SImode)
{ {
...@@ -10364,7 +10364,7 @@ arm_new_rtx_costs (rtx x, enum rtx_code code, enum rtx_code outer_code, ...@@ -10364,7 +10364,7 @@ arm_new_rtx_costs (rtx x, enum rtx_code code, enum rtx_code outer_code,
*cost = COSTS_N_INSNS (1); *cost = COSTS_N_INSNS (1);
*cost += rtx_cost (XEXP (x, 0), code, 0, speed_p); *cost += rtx_cost (XEXP (x, 0), code, 0, speed_p);
if (speed_p) if (speed_p)
*cost += extra_cost->alu.extnd; *cost += extra_cost->alu.extend;
} }
else if (GET_MODE (XEXP (x, 0)) != SImode) else if (GET_MODE (XEXP (x, 0)) != SImode)
{ {
......
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