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Commit 98060bbe by Michael Meissner Committed by Michael Meissner
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vector.md (vec_extract<mode>): Change the calling signature of… 

vector.md (vec_extract<mode>): Change the calling signature of rs6000_expand_vector_extract so that the...

2016-07-27  Michael Meissner  <meissner@linux.vnet.ibm.com>

	* config/rs6000/vector.md (vec_extract<mode>): Change the calling
	signature of rs6000_expand_vector_extract so that the element
	number is a RTX instead of a constant integer.
	* config/rs6000/rs6000-protos.h (rs6000_expand_vector_extract):
	Likewise.
	* config/rs6000/rs6000.c (rs6000_expand_vector_extract): Likewise.
	(altivec_expand_vec_ext_builtin): Likewise.
	* config/rs6000/altivec.md (reduc_plus_scal_<mode>): Likewise.
	* config/rs6000/vsx.md (vsx_extract_<mode>): Fix spelling of the
	MFVSRLD instruction.

From-SVN: r238799
parent 427f68c6
Showing with 37 additions and 18 deletions
gcc/ChangeLog
2016-07-27 Michael Meissner <meissner@linux.vnet.ibm.com>
* config/rs6000/vector.md (vec_extract<mode>): Change the calling
signature of rs6000_expand_vector_extract so that the element
number is a RTX instead of a constant integer.
* config/rs6000/rs6000-protos.h (rs6000_expand_vector_extract):
Likewise.
* config/rs6000/rs6000.c (rs6000_expand_vector_extract): Likewise.
(altivec_expand_vec_ext_builtin): Likewise.
* config/rs6000/altivec.md (reduc_plus_scal_<mode>): Likewise.
* config/rs6000/vsx.md (vsx_extract_<mode>): Fix spelling of the
MFVSRLD instruction.
2016-07-27 David Malcolm <dmalcolm@redhat.com>
* input.c (get_pure_location): Move here from tree.c.
......
gcc/config/rs6000/altivec.md
......@@ -2781,7 +2781,7 @@
emit_insn (gen_altivec_vspltisw (vzero, const0_rtx));
emit_insn (gen_altivec_vsum4s<VI_char>s (vtmp1, operands[1], vzero));
emit_insn (gen_altivec_vsumsws_direct (dest, vtmp1, vzero));
rs6000_expand_vector_extract (operands[0], vtmp2, elt);
rs6000_expand_vector_extract (operands[0], vtmp2, GEN_INT (elt));
DONE;
})
......
gcc/config/rs6000/rs6000-protos.h
......@@ -61,7 +61,7 @@ extern void convert_int_to_float128 (rtx *, enum rtx_code);
extern void rs6000_expand_vector_init (rtx, rtx);
extern void paired_expand_vector_init (rtx, rtx);
extern void rs6000_expand_vector_set (rtx, rtx, int);
extern void rs6000_expand_vector_extract (rtx, rtx, int);
extern void rs6000_expand_vector_extract (rtx, rtx, rtx);
extern bool altivec_expand_vec_perm_const (rtx op[4]);
extern void altivec_expand_vec_perm_le (rtx op[4]);
extern bool rs6000_expand_vec_perm_const (rtx op[4]);
......
gcc/config/rs6000/rs6000.c
......@@ -6911,35 +6911,35 @@ rs6000_expand_vector_set (rtx target, rtx val, int elt)
/* Extract field ELT from VEC into TARGET. */
void
rs6000_expand_vector_extract (rtx target, rtx vec, int elt)
rs6000_expand_vector_extract (rtx target, rtx vec, rtx elt)
{
machine_mode mode = GET_MODE (vec);
machine_mode inner_mode = GET_MODE_INNER (mode);
rtx mem;
if (VECTOR_MEM_VSX_P (mode))
if (VECTOR_MEM_VSX_P (mode) && CONST_INT_P (elt))
{
switch (mode)
{
default:
break;
case V1TImode:
gcc_assert (elt == 0 && inner_mode == TImode);
gcc_assert (INTVAL (elt) == 0 && inner_mode == TImode);
emit_move_insn (target, gen_lowpart (TImode, vec));
break;
case V2DFmode:
emit_insn (gen_vsx_extract_v2df (target, vec, GEN_INT (elt)));
emit_insn (gen_vsx_extract_v2df (target, vec, elt));
return;
case V2DImode:
emit_insn (gen_vsx_extract_v2di (target, vec, GEN_INT (elt)));
emit_insn (gen_vsx_extract_v2di (target, vec, elt));
return;
case V4SFmode:
emit_insn (gen_vsx_extract_v4sf (target, vec, GEN_INT (elt)));
emit_insn (gen_vsx_extract_v4sf (target, vec, elt));
return;
case V16QImode:
if (TARGET_VEXTRACTUB)
{
emit_insn (gen_vsx_extract_v16qi (target, vec, GEN_INT (elt)));
emit_insn (gen_vsx_extract_v16qi (target, vec, elt));
return;
}
else
......@@ -6947,7 +6947,7 @@ rs6000_expand_vector_extract (rtx target, rtx vec, int elt)
case V8HImode:
if (TARGET_VEXTRACTUB)
{
emit_insn (gen_vsx_extract_v8hi (target, vec, GEN_INT (elt)));
emit_insn (gen_vsx_extract_v8hi (target, vec, elt));
return;
}
else
......@@ -6955,7 +6955,7 @@ rs6000_expand_vector_extract (rtx target, rtx vec, int elt)
case V4SImode:
if (TARGET_VEXTRACTUB)
{
emit_insn (gen_vsx_extract_v4si (target, vec, GEN_INT (elt)));
emit_insn (gen_vsx_extract_v4si (target, vec, elt));
return;
}
else
......@@ -6963,13 +6963,16 @@ rs6000_expand_vector_extract (rtx target, rtx vec, int elt)
}
}
gcc_assert (CONST_INT_P (elt));
/* Allocate mode-sized buffer. */
mem = assign_stack_temp (mode, GET_MODE_SIZE (mode));
emit_move_insn (mem, vec);
/* Add offset to field within buffer matching vector element. */
mem = adjust_address_nv (mem, inner_mode, elt * GET_MODE_SIZE (inner_mode));
mem = adjust_address_nv (mem, inner_mode,
INTVAL (elt) * GET_MODE_SIZE (inner_mode));
emit_move_insn (target, adjust_address_nv (mem, inner_mode, 0));
}
......@@ -14658,14 +14661,18 @@ altivec_expand_vec_ext_builtin (tree exp, rtx target)
{
machine_mode tmode, mode0;
tree arg0, arg1;
int elt;
rtx op0;
rtx op1;
arg0 = CALL_EXPR_ARG (exp, 0);
arg1 = CALL_EXPR_ARG (exp, 1);
op0 = expand_normal (arg0);
elt = get_element_number (TREE_TYPE (arg0), arg1);
op1 = expand_normal (arg1);
/* Call get_element_number to validate arg1 if it is a constant. */
if (TREE_CODE (arg1) == INTEGER_CST)
(void) get_element_number (TREE_TYPE (arg0), arg1);
tmode = TYPE_MODE (TREE_TYPE (TREE_TYPE (arg0)));
mode0 = TYPE_MODE (TREE_TYPE (arg0));
......@@ -14676,7 +14683,7 @@ altivec_expand_vec_ext_builtin (tree exp, rtx target)
if (optimize || !target || !register_operand (target, tmode))
target = gen_reg_rtx (tmode);
rs6000_expand_vector_extract (target, op0, elt);
rs6000_expand_vector_extract (target, op0, op1);
return target;
}
gcc/config/rs6000/vector.md
......@@ -858,8 +858,7 @@
(match_operand 2 "const_int_operand" "")]
"VECTOR_MEM_ALTIVEC_OR_VSX_P (<MODE>mode)"
{
rs6000_expand_vector_extract (operands[0], operands[1],
INTVAL (operands[2]));
rs6000_expand_vector_extract (operands[0], operands[1], operands[2]);
DONE;
})
......
gcc/config/rs6000/vsx.md
......@@ -2159,7 +2159,7 @@
else if (element == VECTOR_ELEMENT_MFVSRLD_64BIT && INT_REGNO_P (op0_regno)
&& TARGET_P9_VECTOR && TARGET_POWERPC64 && TARGET_DIRECT_MOVE)
return "mfvsrdl %0,%x1";
return "mfvsrld %0,%x1";
else if (VSX_REGNO_P (op0_regno))
{
......
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