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Commit 97755701 by Alan Lawrence Committed by Alan Lawrence
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[AArch64 array_mode 7/8] Combine the expanders using VSTRUCT:nregs 

	* config/aarch64/aarch64-simd.md (aarch64_ld2r<mode>,
	aarch64_ld3r<mode>, aarch64_ld4r<mode>): Combine together, making...
	(aarch64_simd_ld<VSTRUCT:nregs>r<VALLDIF:mode>): ...this.
	(aarch64_ld2_lane<mode>, aarch64_ld3_lane<mode>,
	aarch64_ld4_lane<mode>): Combine together, making...
	(aarch64_ld<VSTRUCT:nregs>_lane<VALLDIF:mode>): ...this.
	(aarch64_st2_lane<mode>, aarch64_st3_lane<mode>,
	aarch64_st4_lane<mode>): Combine together, making...
	(aarch64_st<VSTRUCT:nregs>_lane<VALLDIF:mode>): ...this.
	* config/aarch64/iterators.md (nregs): Add comment.

From-SVN: r227793
parent 2f3bb934
Showing with 39 additions and 115 deletions
gcc/ChangeLog
2015-09-15 Alan Lawrence <alan.lawrence@arm.com>
* config/aarch64/aarch64-simd.md (aarch64_ld2r<mode>,
aarch64_ld3r<mode>, aarch64_ld4r<mode>): Combine together, making...
(aarch64_simd_ld<VSTRUCT:nregs>r<VALLDIF:mode>): ...this.
(aarch64_ld2_lane<mode>, aarch64_ld3_lane<mode>,
aarch64_ld4_lane<mode>): Combine together, making...
(aarch64_ld<VSTRUCT:nregs>_lane<VALLDIF:mode>): ...this.
(aarch64_st2_lane<mode>, aarch64_st3_lane<mode>,
aarch64_st4_lane<mode>): Combine together, making...
(aarch64_st<VSTRUCT:nregs>_lane<VALLDIF:mode>): ...this.
* config/aarch64/iterators.md (nregs): Add comment.
2015-09-15 Alan Lawrence <alan.lawrence@arm.com>
* config/aarch64/aarch64-simd.md (aarch64_simd_ld2r<mode>):
Change operand mode from <V_TWO_ELEM> to BLK.
(aarch64_vec_load_lanesoi_lane<mode>): Likewise.
......
gcc/config/aarch64/aarch64-simd.md
......@@ -4381,42 +4381,18 @@
FAIL;
})
(define_expand "aarch64_ld2r<mode>"
[(match_operand:OI 0 "register_operand" "=w")
(define_expand "aarch64_ld<VSTRUCT:nregs>r<VALLDIF:mode>"
[(match_operand:VSTRUCT 0 "register_operand" "=w")
(match_operand:DI 1 "register_operand" "w")
(unspec:VALLDIF [(const_int 0)] UNSPEC_VSTRUCTDUMMY)]
"TARGET_SIMD"
{
rtx mem = gen_rtx_MEM (BLKmode, operands[1]);
set_mem_size (mem, GET_MODE_SIZE (GET_MODE_INNER (<MODE>mode)) * 2);
set_mem_size (mem, GET_MODE_SIZE (GET_MODE_INNER (<VALLDIF:MODE>mode))
* <VSTRUCT:nregs>);
emit_insn (gen_aarch64_simd_ld2r<mode> (operands[0], mem));
DONE;
})
(define_expand "aarch64_ld3r<mode>"
[(match_operand:CI 0 "register_operand" "=w")
(match_operand:DI 1 "register_operand" "w")
(unspec:VALLDIF [(const_int 0)] UNSPEC_VSTRUCTDUMMY)]
"TARGET_SIMD"
{
rtx mem = gen_rtx_MEM (BLKmode, operands[1]);
set_mem_size (mem, GET_MODE_SIZE (GET_MODE_INNER (<MODE>mode)) * 3);
emit_insn (gen_aarch64_simd_ld3r<mode> (operands[0], mem));
DONE;
})
(define_expand "aarch64_ld4r<mode>"
[(match_operand:XI 0 "register_operand" "=w")
(match_operand:DI 1 "register_operand" "w")
(unspec:VALLDIF [(const_int 0)] UNSPEC_VSTRUCTDUMMY)]
"TARGET_SIMD"
{
rtx mem = gen_rtx_MEM (BLKmode, operands[1]);
set_mem_size (mem, GET_MODE_SIZE (GET_MODE_INNER (<MODE>mode)) * 4);
emit_insn (gen_aarch64_simd_ld4r<mode> (operands[0],mem));
emit_insn (gen_aarch64_simd_ld<VSTRUCT:nregs>r<VALLDIF:mode> (operands[0],
mem));
DONE;
})
......@@ -4599,62 +4575,26 @@
DONE;
})
(define_expand "aarch64_ld2_lane<mode>"
[(match_operand:OI 0 "register_operand" "=w")
(match_operand:DI 1 "register_operand" "w")
(match_operand:OI 2 "register_operand" "0")
(match_operand:SI 3 "immediate_operand" "i")
(unspec:VALLDIF [(const_int 0)] UNSPEC_VSTRUCTDUMMY)]
"TARGET_SIMD"
{
rtx mem = gen_rtx_MEM (BLKmode, operands[1]);
set_mem_size (mem, GET_MODE_SIZE (GET_MODE_INNER (<MODE>mode)) * 2);
emit_insn (gen_aarch64_vec_load_lanesoi_lane<mode> (operands[0],
mem,
operands[2],
operands[3]));
DONE;
})
(define_expand "aarch64_ld3_lane<mode>"
[(match_operand:CI 0 "register_operand" "=w")
(define_expand "aarch64_ld<VSTRUCT:nregs>_lane<VALLDIF:mode>"
[(match_operand:VSTRUCT 0 "register_operand" "=w")
(match_operand:DI 1 "register_operand" "w")
(match_operand:CI 2 "register_operand" "0")
(match_operand:VSTRUCT 2 "register_operand" "0")
(match_operand:SI 3 "immediate_operand" "i")
(unspec:VALLDIF [(const_int 0)] UNSPEC_VSTRUCTDUMMY)]
"TARGET_SIMD"
{
rtx mem = gen_rtx_MEM (BLKmode, operands[1]);
set_mem_size (mem, GET_MODE_SIZE (GET_MODE_INNER (<MODE>mode)) * 3);
emit_insn (gen_aarch64_vec_load_lanesci_lane<mode> (operands[0],
mem,
operands[2],
operands[3]));
set_mem_size (mem, GET_MODE_SIZE (GET_MODE_INNER (<VALLDIF:MODE>mode))
* <VSTRUCT:nregs>);
aarch64_simd_lane_bounds (operands[3], 0,
GET_MODE_NUNITS (<VALLDIF:MODE>mode),
NULL);
emit_insn (gen_aarch64_vec_load_lanes<VSTRUCT:mode>_lane<VALLDIF:mode> (
operands[0], mem, operands[2], operands[3]));
DONE;
})
(define_expand "aarch64_ld4_lane<mode>"
[(match_operand:XI 0 "register_operand" "=w")
(match_operand:DI 1 "register_operand" "w")
(match_operand:XI 2 "register_operand" "0")
(match_operand:SI 3 "immediate_operand" "i")
(unspec:VALLDIF [(const_int 0)] UNSPEC_VSTRUCTDUMMY)]
"TARGET_SIMD"
{
rtx mem = gen_rtx_MEM (BLKmode, operands[1]);
set_mem_size (mem, GET_MODE_SIZE (GET_MODE_INNER (<MODE>mode)) * 4);
emit_insn (gen_aarch64_vec_load_lanesxi_lane<mode> (operands[0],
mem,
operands[2],
operands[3]));
DONE;
})
;; Expanders for builtins to extract vector registers from large
;; opaque integer modes.
......@@ -4882,51 +4822,19 @@
DONE;
})
(define_expand "aarch64_st2_lane<mode>"
[(match_operand:DI 0 "register_operand" "r")
(match_operand:OI 1 "register_operand" "w")
(unspec:VALLDIF [(const_int 0)] UNSPEC_VSTRUCTDUMMY)
(match_operand:SI 2 "immediate_operand")]
"TARGET_SIMD"
{
rtx mem = gen_rtx_MEM (BLKmode, operands[0]);
set_mem_size (mem, GET_MODE_SIZE (GET_MODE_INNER (<MODE>mode)) * 2);
emit_insn (gen_aarch64_vec_store_lanesoi_lane<mode> (mem,
operands[1],
operands[2]));
DONE;
})
(define_expand "aarch64_st3_lane<mode>"
[(match_operand:DI 0 "register_operand" "r")
(match_operand:CI 1 "register_operand" "w")
(unspec:VALLDIF [(const_int 0)] UNSPEC_VSTRUCTDUMMY)
(match_operand:SI 2 "immediate_operand")]
"TARGET_SIMD"
{
rtx mem = gen_rtx_MEM (BLKmode, operands[0]);
set_mem_size (mem, GET_MODE_SIZE (GET_MODE_INNER (<MODE>mode)) * 3);
emit_insn (gen_aarch64_vec_store_lanesci_lane<mode> (mem,
operands[1],
operands[2]));
DONE;
})
(define_expand "aarch64_st4_lane<mode>"
(define_expand "aarch64_st<VSTRUCT:nregs>_lane<VALLDIF:mode>"
[(match_operand:DI 0 "register_operand" "r")
(match_operand:XI 1 "register_operand" "w")
(match_operand:VSTRUCT 1 "register_operand" "w")
(unspec:VALLDIF [(const_int 0)] UNSPEC_VSTRUCTDUMMY)
(match_operand:SI 2 "immediate_operand")]
"TARGET_SIMD"
{
rtx mem = gen_rtx_MEM (BLKmode, operands[0]);
set_mem_size (mem, GET_MODE_SIZE (GET_MODE_INNER (<MODE>mode)) * 4);
set_mem_size (mem, GET_MODE_SIZE (GET_MODE_INNER (<VALLDIF:MODE>mode))
* <VSTRUCT:nregs>);
emit_insn (gen_aarch64_vec_store_lanesxi_lane<mode> (mem,
operands[1],
operands[2]));
emit_insn (gen_aarch64_vec_store_lanes<VSTRUCT:mode>_lane<VALLDIF:mode> (
mem, operands[1], operands[2]));
DONE;
})
......
gcc/config/aarch64/iterators.md
......@@ -577,6 +577,9 @@
(define_mode_attr Vendreg [(OI "T") (CI "U") (XI "V")])
;; This is both the number of Q-Registers needed to hold the corresponding
;; opaque large integer mode, and the number of elements touched by the
;; ld..._lane and st..._lane operations.
(define_mode_attr nregs [(OI "2") (CI "3") (XI "4")])
(define_mode_attr VRL2 [(V8QI "V32QI") (V4HI "V16HI")
......
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