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lvzhengyang
riscv-gcc-1
Commits
97532d1a
Commit
97532d1a
authored
Aug 31, 2015
by
Michael Collison
Committed by
Michael Collison
Aug 31, 2015
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Rename [su]sum_widen to widen_[su]sum to reflect correct standard names.
From-SVN: r227333
parent
8f98def6
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+10
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gcc/ChangeLog
+6
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gcc/doc/md.texi
+4
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gcc/ChangeLog
View file @
97532d1a
2015
-
08
-
30
Michael
Collison
<
michael
.
collison
@
linaro
.
org
>
PR
other
/
67320
*
doc
.
md
.
texi
:
Rename
[
su
]
sum_widen
to
widen_
[
su
]
sum
to
reflect
correct
standard
names
2015
-
08
-
30
Bill
Schmidt
<
wschmidt
@
linux
.
vnet
.
ibm
.
com
>
*
config
/
rs6000
/
rs6000
.
c
(
swap_web_entry
):
Enlarge
...
...
gcc/doc/md.texi
View file @
97532d1a
...
...
@@ -4946,10 +4946,10 @@ is of a wider mode, is computed and added to operand 3. Operand 3 is of a mode
equal or wider than the mode of the absolute difference. The result is placed
in operand 0, which is of the same mode as operand 3.
@cindex @code{
ssum_widen
@var{m3}} instruction pattern
@item @samp{
ssum_widen
@var{m3}}
@cindex @code{
usum_widen
@var{m3}} instruction pattern
@itemx @samp{
usum_widen
@var{m3}}
@cindex @code{
widen_ssum
@var{m3}} instruction pattern
@item @samp{
widen_ssum
@var{m3}}
@cindex @code{
widen_usum
@var{m3}} instruction pattern
@itemx @samp{
widen_usum
@var{m3}}
Operands 0 and 2 are of the same mode, which is wider than the mode of
operand 1. Add operand 1 to operand 2 and place the widened result in
operand 0. (This is used express accumulation of elements into an accumulator
...
...
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