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lvzhengyang
riscv-gcc-1
Commits
95ac8e67
Commit
95ac8e67
authored
Sep 19, 1992
by
Richard Kenner
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(smax, smin, umax, umin): Add define_splits.
From-SVN: r2169
parent
df3d94ed
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gcc/config/rs6000/rs6000.md
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gcc/config/rs6000/rs6000.md
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95ac8e67
...
...
@@ -271,7 +271,8 @@
;; For SMIN, SMAX, UMIN, and UMAX, we use DEFINE_EXPAND's that involve a doz
[
i
]
;; instruction and some auxiliary computations. Then we just have a single
;; DEFINE_INSN for doz
[
i
]
.
;; DEFINE_INSN for doz
[
i
]
and the define_splits to make them if made by
;; combine.
(define_expand "sminsi3"
[
(set (match_dup 3)
...
...
@@ -285,6 +286,19 @@
"
{ operands
[
3
]
= gen_reg_rtx (SImode); }")
(define_split
[
(set (match_operand:SI 0 "gpc_reg_operand" "")
(smin:SI (match_operand:SI 1 "gpc_reg_operand" "")
(match_operand:SI 2 "reg_or_short_operand" "")))
(clobber (match_operand:SI 3 "gpc_reg_operand" ""))]
""
[
(set (match_dup 3)
(if_then_else:SI (gt:SI (match_dup 1) (match_dup 2))
(const_int 0)
(minus:SI (match_dup 2) (match_dup 1))))
(set (match_dup 0) (minus:SI (match_dup 2) (match_dup 3)))]
"")
(define_expand "smaxsi3"
[
(set (match_dup 3)
(if_then_else:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "")
...
...
@@ -297,6 +311,19 @@
"
{ operands
[
3
]
= gen_reg_rtx (SImode); }")
(define_split
[
(set (match_operand:SI 0 "gpc_reg_operand" "")
(smax:SI (match_operand:SI 1 "gpc_reg_operand" "")
(match_operand:SI 2 "reg_or_short_operand" "")))
(clobber (match_operand:SI 3 "gpc_reg_operand" ""))]
""
[
(set (match_dup 3)
(if_then_else:SI (gt:SI (match_dup 1) (match_dup 2))
(const_int 0)
(minus:SI (match_dup 2) (match_dup 1))))
(set (match_dup 0) (plus:SI (match_dup 3) (match_dup 1)))]
"")
(define_expand "uminsi3"
[
(set (match_dup 3) (xor:SI (match_operand:SI 1 "gpc_reg_operand" "")
(const_int -2147483648)))
...
...
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