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Commit 9595a419 by Nick Clifton Committed by Nick Clifton
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predicates.md (rx_store_multiple_vector): Reverse order of expected registers. 

        * config/rx/predicates.md (rx_store_multiple_vector): Reverse
        order of expected registers.
        (rx_load_multiple_vector): Likewise.
        (rx_rtsd_vector): Likewise.
        * config/rx/rx.c (rx_cpu_type): New variable.
        (rx_print_operand): Fix bug printing 64-bit constant values.
        (rx_emit_stack_pushm): Reverse order of pushed registers.
        (gen_rx_store_vector): Likewise.
        (is_fast_interrupt_func): Only accept "fast_interrupt" as the
        attribute name.
        (is_exception_func): Rename to is_interrupt_func and only accept
        "interrupt" as the attribute name.
        (rx_get_stack_layout): Use new function name.
        (rx_func_attr_inlinable): Likewise.
        (rx_attribute_table): Remove "exception".
        (rx_expand_prologue): If necessary push the accumulator register
        in the prologue of interrupt functions.
        (rx_expand_epilogue): If necessary pop the accumulator.
        (rx_builtins): Add RX_BUILTIN_MVTIPL.
        (rx_expand_builtin_stz): Remove.
        (rx_expand_builtin_mvtipl): New function.
        (rx_init_builtins): Handle RX_BUILTIN_MVTIPL.
        (rx_expand_builtin): Likewise.
        (rx_enable_fpu): New variable.
        (rx_handle_option): Handle -fpu, -nofpu, -mcpu and -patch.
        * config/rx/rx.h (TARGET_CPU_CPP_BUILTINS): Assert machine based
        on rx_cpu_type.  Define __RX_FPU_INSNS__ if FPU insns are allowed.
        (enum rx_cpu_types): Define.
        (ASM_SPEC): Pass -m32bit-doubles on to assembler.
        (INCOMING_FRAME_SP_OFFSET): Define.
        (ARG_POINTER_CFA_OFFSET): Define.
        (FRAME_POINTER_CFA_OFFSET): Define.
        (OVERRIDE_OPTIONS): Enable fast math if RX FPU insns are enabled.
        (ALLOW_RX_FPU_INSNS): Define.
        * config/rx/rx.md: Test ALLOW_RX_FPU_INSNS instead of
        fast_math_flags_set_p.
        (UNSPEC_BUILTIN_MVTIPL): Define.
        (revl): Rename to bswapsi2.
        (bswaphi2): New pattern.
        (mvtachi): Mark as volatile because it uses a register unknown to
        GCC.
        (mvtaclo): Likewise.
        (racw): Likewise.
        (mvtc): Remove clobber of cc0.
        (mvtcp): Delete.
        (opecp): Delete.
        * config/rx/rx.opt (mieee): Remove.
        (fpu): Add.
        (nofpu): Add.
        (mcpu=): Add.
        (patch=): Add.
        (msave-acc-in-interrupts): Add.
        * config/rx/t-rx (MULTILIB_OPTIONS): Change default to 64bit
        doubles.
        (MULTILIB_DIRS): Likewise.
        (MULTILIB_MATCHES): Treat -fpu as an alias for -m32bit-doubles.
        * doc/extend.texi: Remove description of "exception" function
        attribute.
        * doc/invoke.texi: Document -fpu, -nofpu, -mcpu=, -patch= and
        -msave-acc-in-interrupts options.

        * gcc.target/rx/builtins,c: Remove redundant tests.
        Add test of MVTIPL instruction.
        * gcc.target/rx/interrupts.c: Use fast_interrupt and interrupt
        function attributes.  Add -msave-acc-in-interrupts option to the
        command line.

Co-Authored-By: Kevin Buettner <kevinb@redhat.com>

From-SVN: r153853
parent 48d3ee1d
Showing with 248 additions and 96 deletions
gcc/ChangeLog
2009-11-03 Nick Clifton <nickc@redhat.com>
Kevin Buettner <kevinb@redhat.com>
* config/rx/predicates.md (rx_store_multiple_vector): Reverse
order of expected registers.
(rx_load_multiple_vector): Likewise.
(rx_rtsd_vector): Likewise.
* config/rx/rx.c (rx_cpu_type): New variable.
(rx_print_operand): Fix bug printing 64-bit constant values.
(rx_emit_stack_pushm): Reverse order of pushed registers.
(gen_rx_store_vector): Likewise.
(is_fast_interrupt_func): Only accept "fast_interrupt" as the
attribute name.
(is_exception_func): Rename to is_interrupt_func and only accept
"interrupt" as the attribute name.
(rx_get_stack_layout): Use new function name.
(rx_func_attr_inlinable): Likewise.
(rx_attribute_table): Remove "exception".
(rx_expand_prologue): If necessary push the accumulator register
in the prologue of interrupt functions.
(rx_expand_epilogue): If necessary pop the accumulator.
(rx_builtins): Add RX_BUILTIN_MVTIPL.
(rx_expand_builtin_stz): Remove.
(rx_expand_builtin_mvtipl): New function.
(rx_init_builtins): Handle RX_BUILTIN_MVTIPL.
(rx_expand_builtin): Likewise.
(rx_enable_fpu): New variable.
(rx_handle_option): Handle -fpu, -nofpu, -mcpu and -patch.
* config/rx/rx.h (TARGET_CPU_CPP_BUILTINS): Assert machine based
on rx_cpu_type. Define __RX_FPU_INSNS__ if FPU insns are allowed.
(enum rx_cpu_types): Define.
(ASM_SPEC): Pass -m32bit-doubles on to assembler.
(INCOMING_FRAME_SP_OFFSET): Define.
(ARG_POINTER_CFA_OFFSET): Define.
(FRAME_POINTER_CFA_OFFSET): Define.
(OVERRIDE_OPTIONS): Enable fast math if RX FPU insns are enabled.
(ALLOW_RX_FPU_INSNS): Define.
* config/rx/rx.md: Test ALLOW_RX_FPU_INSNS instead of
fast_math_flags_set_p.
(UNSPEC_BUILTIN_MVTIPL): Define.
(revl): Rename to bswapsi2.
(bswaphi2): New pattern.
(mvtachi): Mark as volatile because it uses a register unknown to
GCC.
(mvtaclo): Likewise.
(racw): Likewise.
(mvtc): Remove clobber of cc0.
(mvtcp): Delete.
(opecp): Delete.
* config/rx/rx.opt (mieee): Remove.
(fpu): Add.
(nofpu): Add.
(mcpu=): Add.
(patch=): Add.
(msave-acc-in-interrupts): Add.
* config/rx/t-rx (MULTILIB_OPTIONS): Change default to 64bit
doubles.
(MULTILIB_DIRS): Likewise.
(MULTILIB_MATCHES): Treat -fpu as an alias for -m32bit-doubles.
* doc/extend.texi: Remove description of "exception" function
attribute.
* doc/invoke.texi: Document -fpu, -nofpu, -mcpu=, -patch= and
-msave-acc-in-interrupts options.
2009-11-03 Richard Guenther <rguenther@suse.de>
* c-common.c (fold_offsetof_1): Use HOST_WIDE_INT_PRINT_DEC.
gcc/config/rx/constraints.md
......@@ -55,7 +55,7 @@
;; This constraint is used by the SUBSI3 pattern because the
;; RX SUB instruction can only take a 4-bit unsigned integer
;; value.
;; value. Also used by the MVTIPL instruction.
(define_constraint "Uint04"
"@internal An unsigned 4-bit immediate value"
(and (match_code "const_int")
......
gcc/config/rx/predicates.md
......@@ -117,16 +117,22 @@
/* Check that the next element is the first push. */
element = XVECEXP (op, 0, 1);
if ( ! SET_P (element)
|| ! REG_P (SET_SRC (element))
|| GET_MODE (SET_SRC (element)) != SImode
|| ! MEM_P (SET_DEST (element))
|| ! REG_P (XEXP (SET_DEST (element), 0))
|| REGNO (XEXP (SET_DEST (element), 0)) != SP_REG
|| ! REG_P (SET_SRC (element)))
|| GET_MODE (SET_DEST (element)) != SImode
|| GET_CODE (XEXP (SET_DEST (element), 0)) != MINUS
|| ! REG_P (XEXP (XEXP (SET_DEST (element), 0), 0))
|| REGNO (XEXP (XEXP (SET_DEST (element), 0), 0)) != SP_REG
|| ! CONST_INT_P (XEXP (XEXP (SET_DEST (element), 0), 1))
|| INTVAL (XEXP (XEXP (SET_DEST (element), 0), 1))
!= GET_MODE_SIZE (SImode))
return false;
src_regno = REGNO (SET_SRC (element));
/* Check that the remaining elements use SP-<disp>
addressing and incremental register numbers. */
addressing and decreasing register numbers. */
for (i = 2; i < count; i++)
{
element = XVECEXP (op, 0, i);
......@@ -134,7 +140,7 @@
if ( ! SET_P (element)
|| ! REG_P (SET_SRC (element))
|| GET_MODE (SET_SRC (element)) != SImode
|| REGNO (SET_SRC (element)) != src_regno + (i - 1)
|| REGNO (SET_SRC (element)) != src_regno - (i - 1)
|| ! MEM_P (SET_DEST (element))
|| GET_MODE (SET_DEST (element)) != SImode
|| GET_CODE (XEXP (SET_DEST (element), 0)) != MINUS
......@@ -142,7 +148,7 @@
|| REGNO (XEXP (XEXP (SET_DEST (element), 0), 0)) != SP_REG
|| ! CONST_INT_P (XEXP (XEXP (SET_DEST (element), 0), 1))
|| INTVAL (XEXP (XEXP (SET_DEST (element), 0), 1))
!= (i - 1) * GET_MODE_SIZE (SImode))
!= i * GET_MODE_SIZE (SImode))
return false;
}
return true;
......
gcc/config/rx/rx.h
......@@ -24,18 +24,24 @@
{ \
builtin_define ("__RX__"); \
builtin_assert ("cpu=RX"); \
builtin_assert ("machine=RX"); \
if (rx_cpu_type == RX610) \
builtin_assert ("machine=RX610"); \
else \
builtin_assert ("machine=RX600"); \
\
if (TARGET_BIG_ENDIAN_DATA) \
builtin_define ("__RX_BIG_ENDIAN__"); \
else \
builtin_define ("__RX_LITTLE_ENDIAN__");\
\
if (TARGET_64BIT_DOUBLES) \
builtin_define ("__RX_64BIT_DOUBLES__");\
else \
if (TARGET_32BIT_DOUBLES) \
builtin_define ("__RX_32BIT_DOUBLES__");\
else \
builtin_define ("__RX_64BIT_DOUBLES__");\
\
if (ALLOW_RX_FPU_INSNS) \
builtin_define ("__RX_FPU_INSNS__"); \
\
if (TARGET_AS100_SYNTAX) \
builtin_define ("__RX_AS100_SYNTAX__"); \
else \
......@@ -43,6 +49,17 @@
} \
while (0)
enum rx_cpu_types
{
RX600,
RX610
};
extern enum rx_cpu_types rx_cpu_type;
#undef CC1_SPEC
#define CC1_SPEC "%{mas100-syntax:%{gdwarf*:%e-mas100-syntax is incompatible with -gdwarf}}"
#undef STARTFILE_SPEC
#define STARTFILE_SPEC "%{pg:gcrt0.o%s}%{!pg:crt0.o%s} crtbegin.o%s"
......@@ -52,7 +69,8 @@
#undef ASM_SPEC
#define ASM_SPEC "\
%{mbig-endian-data:-mbig-endian-data} \
%{m64bit-doubles:-m64bit-doubles} \
%{m32bit-doubles:-m32bit-doubles} \
%{!m32bit-doubles:-m64bit-doubles} \
%{msmall-data-limit*:-msmall-data-limit} \
%{mrelax:-relax} \
"
......@@ -88,16 +106,17 @@
#define LONG_LONG_TYPE_SIZE 64
#define FLOAT_TYPE_SIZE 32
#define DOUBLE_TYPE_SIZE (TARGET_64BIT_DOUBLES ? 64 : 32)
#define DOUBLE_TYPE_SIZE (TARGET_32BIT_DOUBLES ? 32 : 64)
#define LONG_DOUBLE_TYPE_SIZE DOUBLE_TYPE_SIZE
#ifdef __RX_64BIT_DOUBLES__
#define LIBGCC2_LONG_DOUBLE_TYPE_SIZE 64
#define LIBGCC2_DOUBLE_TYPE_SIZE 64
#define LIBGCC2_HAS_DF_MODE 1
#else
#ifdef __RX_32BIT_DOUBLES__
#define LIBGCC2_HAS_DF_MODE 0
#define LIBGCC2_LONG_DOUBLE_TYPE_SIZE 32
#define LIBGCC2_DOUBLE_TYPE_SIZE 32
#else
#define LIBGCC2_HAS_DF_MODE 1
#define LIBGCC2_LONG_DOUBLE_TYPE_SIZE 64
#define LIBGCC2_DOUBLE_TYPE_SIZE 64
#endif
#define DEFAULT_SIGNED_CHAR 0
......@@ -591,7 +610,6 @@ typedef unsigned int CUMULATIVE_ARGS;
#define PRINT_OPERAND_ADDRESS(FILE, ADDR) \
rx_print_operand_address (FILE, ADDR)
#define CC_NO_CARRY 0400
#define NOTICE_UPDATE_CC(EXP, INSN) rx_notice_update_cc (EXP, INSN)
......@@ -614,19 +632,28 @@ extern int rx_float_compare_mode;
#define PREFERRED_DEBUGGING_TYPE (TARGET_AS100_SYNTAX \
? DBX_DEBUG : DWARF2_DEBUG)
#undef CC1_SPEC
#define CC1_SPEC "%{mas100-syntax:%{gdwarf*:%e-mas100-syntax is incompatible with -gdwarf}}"
#define INCOMING_FRAME_SP_OFFSET 4
#define ARG_POINTER_CFA_OFFSET(FNDECL) 4
#define FRAME_POINTER_CFA_OFFSET(FNDECL) 4
extern int rx_enable_fpu;
/* For some unknown reason LTO compression is not working, at
least on my local system. So set the default compression
level to none, for now. */
level to none, for now.
For an explanation of rx_flag_no_fpu see rx_handle_option(). */
#define OVERRIDE_OPTIONS \
do \
{ \
if (flag_lto_compression_level == -1) \
flag_lto_compression_level = 0; \
\
if (rx_enable_fpu == 1) \
set_fast_math_flags (true); \
} \
while (0)
/* This macro is used to decide when RX FPU instructions can be used. */
#define ALLOW_RX_FPU_INSNS flag_unsafe_math_optimizations
#define ALLOW_RX_FPU_INSNS ((rx_enable_fpu != -1) \
&& flag_unsafe_math_optimizations)
gcc/config/rx/rx.md
......@@ -27,8 +27,8 @@
;; This code iterator is used for sign- and zero- extensions.
(define_mode_iterator small_int_modes [(HI "") (QI "")])
;; We do not handle DFmode here because by default it is
;; the same as SFmode, and if -m64bit-doubles is active
;; We do not handle DFmode here because it is either
;; the same as SFmode, or if -m64bit-doubles is active
;; then all operations on doubles have to be handled by
;; library functions.
(define_mode_iterator register_modes
......@@ -75,15 +75,14 @@
(UNSPEC_BUILTIN_MVTACHI 41)
(UNSPEC_BUILTIN_MVTACLO 42)
(UNSPEC_BUILTIN_MVTC 43)
(UNSPEC_BUILTIN_MVTCP 44)
(UNSPEC_BUILTIN_OPEPC 45)
(UNSPEC_BUILTIN_RACW 46)
(UNSPEC_BUILTIN_REVW 47)
(UNSPEC_BUILTIN_RMPA 48)
(UNSPEC_BUILTIN_ROUND 49)
(UNSPEC_BUILTIN_SAT 50)
(UNSPEC_BUILTIN_SETPSW 51)
(UNSPEC_BUILTIN_WAIT 52)
(UNSPEC_BUILTIN_MVTIPL 44)
(UNSPEC_BUILTIN_RACW 45)
(UNSPEC_BUILTIN_REVW 46)
(UNSPEC_BUILTIN_RMPA 47)
(UNSPEC_BUILTIN_ROUND 48)
(UNSPEC_BUILTIN_SAT 49)
(UNSPEC_BUILTIN_SETPSW 50)
(UNSPEC_BUILTIN_WAIT 51)
]
)
......@@ -1002,10 +1001,8 @@
(set_attr "timings" "11,11,11,11,11,33")
(set_attr "length" "3,4,5,6,7,6")]
)
;; Floating Point Instructions
;; These patterns are only enabled with -ffast-math because the RX FPU
;; cannot handle sub-normal values.
(define_insn "addsf3"
[(set (match_operand:SF 0 "register_operand" "=r,r,r")
......@@ -1298,7 +1295,6 @@
[(set_attr "length" "3,6")
(set_attr "timings" "22")]
)
;; Block move functions.
......@@ -1580,8 +1576,8 @@
;; Move to Accumulator (high)
(define_insn "mvtachi"
[(unspec:SI [(match_operand:SI 0 "register_operand" "r")]
UNSPEC_BUILTIN_MVTACHI)]
[(unspec_volatile:SI [(match_operand:SI 0 "register_operand" "r")]
UNSPEC_BUILTIN_MVTACHI)]
""
"mvtachi\t%0"
[(set_attr "length" "3")]
......@@ -1589,8 +1585,8 @@
;; Move to Accumulator (low)
(define_insn "mvtaclo"
[(unspec:SI [(match_operand:SI 0 "register_operand" "r")]
UNSPEC_BUILTIN_MVTACLO)]
[(unspec_volatile:SI [(match_operand:SI 0 "register_operand" "r")]
UNSPEC_BUILTIN_MVTACLO)]
""
"mvtaclo\t%0"
[(set_attr "length" "3")]
......@@ -1598,8 +1594,8 @@
;; Round Accumulator
(define_insn "racw"
[(unspec:SI [(match_operand:SI 0 "immediate_operand" "i")]
UNSPEC_BUILTIN_RACW)]
[(unspec_volatile:SI [(match_operand:SI 0 "immediate_operand" "i")]
UNSPEC_BUILTIN_RACW)]
""
"racw\t%0"
[(set_attr "length" "3")]
......@@ -1679,7 +1675,7 @@
;; Move from control register
(define_insn "mvfc"
[(set (match_operand:SI 0 "register_operand" "=r")
[(set (match_operand:SI 0 "register_operand" "=r")
(unspec:SI [(match_operand:SI 1 "immediate_operand" "i")]
UNSPEC_BUILTIN_MVFC))]
""
......@@ -1691,13 +1687,24 @@
(define_insn "mvtc"
[(unspec:SI [(match_operand:SI 0 "immediate_operand" "i,i")
(match_operand:SI 1 "nonmemory_operand" "r,i")]
UNSPEC_BUILTIN_MVTC)
(clobber (cc0))]
UNSPEC_BUILTIN_MVTC)]
""
"mvtc\t%1, %C0"
[(set_attr "length" "3,7")
(set_attr "cc" "clobber")] ;; Just in case the control
;; register selected is the psw.
[(set_attr "length" "3,7")]
;; Ignore possible clobbering of the comparison flags in the
;; PSW register. This is a cc0 target so any cc0 setting
;; instruction will always be paired with a cc0 user, without
;; the possibility of this instruction being placed in between
;; them.
)
;; Move to interrupt priority level
(define_insn "mvtipl"
[(unspec:SI [(match_operand:SI 0 "immediate_operand" "Uint04")]
UNSPEC_BUILTIN_MVTIPL)]
""
"mvtipl\t%0"
[(set_attr "length" "3")]
)
;;---------- Interrupts ------------------------
......@@ -1748,27 +1755,6 @@
[(set_attr "length" "5")]
)
;; Move to co-processor register
(define_insn "mvtcp"
[(unspec:SI [(match_operand:SI 0 "immediate_operand" "i,i")
(match_operand:SI 1 "nonmemory_operand" "i,r")
(match_operand:SI 2 "immediate_operand" "i,i")]
UNSPEC_BUILTIN_MVTCP)]
""
"; mvtcp\t%0, %1, %2"
[(set_attr "length" "7,5")]
)
;; Co-processor operation
(define_insn "opecp"
[(unspec:SI [(match_operand:SI 0 "immediate_operand" "i")
(match_operand:SI 1 "immediate_operand" "i")]
UNSPEC_BUILTIN_OPEPC)]
""
"; opecp\t%0, %1"
[(set_attr "length" "5")]
)
;;---------- Misc ------------------------
;; Required by cfglayout.c...
......
gcc/config/rx/rx.opt
......@@ -19,13 +19,31 @@
; <http://www.gnu.org/licenses/>.
;---------------------------------------------------
m32bit-doubles
Target RejectNegative Mask(32BIT_DOUBLES)
Stores doubles in 32 bits.
m64bit-doubles
Target RejectNegative Mask(64BIT_DOUBLES)
Store doubles in 64 bits.
Target RejectNegative InverseMask(32BIT_DOUBLES)
Store doubles in 64 bits. This is the default.
m32bit-doubles
Target RejectNegative InverseMask(64BIT_DOUBLES)
Stores doubles in 32 bits. This is the default.
fpu
Target RejectNegative Mask(32BIT_DOUBLES) MaskExists
Enable the use of RX FPU instructions.
nofpu
Target RejectNegative InverseMask(32BIT_DOUBLES) MaskExists
Disable the use of RX FPU instructions.
;---------------------------------------------------
mcpu=
Target RejectNegative Joined Var(rx_cpu_name)
Specify the target RX cpu type.
patch=
Target RejectNegative Joined Var(rx_cpu_name)
Alias for -mcpu.
;---------------------------------------------------
......@@ -72,3 +90,9 @@ Maximum size in bytes of constant values allowed as operands.
mint-register=
Target RejectNegative Joined UInteger Var(rx_interrupt_registers) Init(0)
Specifies the number of registers to reserve for interrupt handlers.
;---------------------------------------------------
msave-acc-in-interrupts
Target Mask(SAVE_ACC_REGISTER)
Specifies whether interrupt functions should save and restore the accumulator register.
gcc/config/rx/t-rx
......@@ -20,9 +20,9 @@
# Enable multilibs:
MULTILIB_OPTIONS = m64bit-doubles mbig-endian-data
MULTILIB_DIRNAMES = 64fp big-endian-data
MULTILIB_MATCHES = m64bit-doubles=mieee
MULTILIB_OPTIONS = m32bit-doubles mbig-endian-data
MULTILIB_DIRNAMES = 32fp big-endian-data
MULTILIB_MATCHES = m32bit-doubles=fpu
MULTILIB_EXCEPTIONS =
MULTILIB_EXTRA_OPTS =
......
gcc/doc/extend.texi
......@@ -2270,13 +2270,6 @@ on data in the eight bit data area. Note the eight bit data area is limited to
You must use GAS and GLD from GNU binutils version 2.7 or later for
this attribute to work correctly.
@item exception
@cindex exception handler functions on the RX processor
Use this attribute on the RX to indicate that the specified function
is an exception handler. The compiler will generate function entry and
exit sequences suitable for use in an exception handler when this
attribute is present.
@item exception_handler
@cindex exception handler functions on the Blackfin processor
Use this attribute on the Blackfin to indicate that the specified function
......
gcc/doc/invoke.texi
......@@ -784,14 +784,16 @@ See RS/6000 and PowerPC Options.
-msdata=@var{opt} -mvxworks -G @var{num} -pthread}
@emph{RX Options}
@gccoptlist{-m64bit-doubles -m32bit-doubles -mieee -mno-ieee@gol
@gccoptlist{-m64bit-doubles -m32bit-doubles -fpu -nofpu@gol
-mcpu= -patch=@gol
-mbig-endian-data -mlittle-endian-data @gol
-msmall-data @gol
-msim -mno-sim@gol
-mas100-syntax -mno-as100-syntax@gol
-mrelax@gol
-mmax-constant-size=@gol
-mint-register=}
-mint-register=@gol
-msave-acc-in-interrupts}
@emph{S/390 and zSeries Options}
@gccoptlist{-mtune=@var{cpu-type} -march=@var{cpu-type} @gol
......@@ -15408,16 +15410,37 @@ These @option{-m} options are defined for RX implementations:
@table @gcctabopt
@item -m64bit-doubles
@itemx -m32bit-doubles
@itemx -fpu
@itemx -nofpu
@opindex m64bit-doubles
@opindex m32bit-doubles
@opindex fpu
@opindex nofpu
Make the @code{double} data type be 64-bits (@option{-m64bit-doubles})
or 32-bits (@option{-m32bit-doubles}) in size. The default is
@option{-m32bit-doubles}. @emph{Note} the RX's hardware floating
@option{-m64bit-doubles}. @emph{Note} the RX's hardware floating
point instructions are only used for 32-bit floating point values, and
then only if @option{-ffast-math} has been specified on the command
line. This is because the RX FPU instructions do not properly support
denormal (or sub-normal) values.
The options @option{-fpu} and @option{-nofpu} have been provided at
the request of Rensas for compatibility with their toolchain. The
@option{-mfpu} option enables the use of RX FPU instructions by
selecting 32-bit doubles and enabling unsafe math optimizations. The
@option{-mnofpu} option disables the use of RX FPU instructions, even
if @option{-m32bit-doubles} is active and unsafe math optimizations
have been enabled.
@item -mcpu=@var{name}
@itemx -patch=@var{name}
@opindex -mcpu
@opindex -patch
Selects the type of RX CPU to be targeted. Currently on two types are
supported, the generic @var{RX600} and the specific @var{RX610}. The
only difference between them is that the @var{RX610} does not support
the @code{MVTIPL} instruction.
@item -mbig-endian-data
@itemx -mlittle-endian-data
@opindex mbig-endian-data
......@@ -15493,6 +15516,15 @@ of fast interrupt handlers. A value of 2 reserves @code{r13} and
@code{r12}. A value of 3 reserves @code{r13}, @code{r12} and
@code{r11}, and a value of 4 reserves @code{r13} through @code{r10}.
A value of 0, the default, does not reserve any registers.
@item -msave-acc-in-interrupts
@opindex msave-acc-in-interrupts
Specifies that interrupt handler functions should preserve the
accumulator register. This is only necessary if normal code might use
the accumulator register, for example because it performs 64-bit
multiplications. The default is to ignore the accumulator as this
makes the interrupt handlers faster.
@end table
@emph{Note:} The generic GCC command line @option{-ffixed-@var{reg}}
......
gcc/testsuite/ChangeLog
2009-11-03 Nick Clifton <nickc@redhat.com>
* gcc.target/rx/builtins,c: Remove redundant tests.
Add test of MVTIPL instruction.
* gcc.target/rx/interrupts.c: Use fast_interrupt and interrupt
function attributes. Add -msave-acc-in-interrupts option to the
command line.
2009-11-03 Andrew Stubbs <ams@codesourcery.com>
Maxim Kuvyrkov <maxim@codesourcery.com>
......
gcc/testsuite/gcc.target/rx/builtins.c
......@@ -17,7 +17,6 @@
to correctly set the psw flags. */
int saturate_add (int, int) __attribute__((__noinline__));
int subtract_with_borrow (int, int, int) __attribute__((__noinline__));
int exchange (int, int) __attribute__((__noinline__));
int
......@@ -33,6 +32,13 @@ saturate_add (int arg1, int arg2)
return __builtin_rx_sat (arg1);
}
int
exchange (int arg1, int arg2)
{
arg1 = __builtin_rx_xchg (arg2);
return arg1;
}
long
multiply_and_accumulate (long arg1, long arg2, long arg3)
{
......@@ -157,3 +163,9 @@ rmpa (int * multiplicand, int * multiplier, int num)
{
__builtin_rx_rmpa ();
}
void
set_interrupts (void)
{
__builtin_mvtipl (3);
}
gcc/testsuite/gcc.target/rx/interrupts.c
/* { dg-do compile } */
/* { dg-options "-mint-register=3" } */
/* { dg-options "-mint-register=3 -msave-acc-in-interrupts" } */
/* Verify that the RX specific function attributes work. */
void fast_interrupt (void) __attribute__((__fast_interrupt__));
void interrupt (void) __attribute__((__interrupt__));
void exception (void) __attribute__((__exception__));
int naked (int) __attribute__((__naked__));
int flag = 0;
......@@ -13,16 +13,16 @@ int flag = 0;
by the -fixed-xxx gcc command line option. Returns via RTFI. */
void
interrupt (void)
fast_interrupt (void)
{
flag = 1;
}
/* Exception handler. Must preserve any register it uses, even
/* Interrupt handler. Must preserve any register it uses, even
call clobbered ones. Returns via RTE. */
void
exception (void)
interrupt (void)
{
switch (flag)
{
......
gcc/testsuite/gcc.target/rx/rx-abi-function-tests.c
/* { dg-do run } */
/* { dg-options "-msim" } */
/* Note: The -msim abiove is actually there to override the default
/* Note: The -msim above is actually there to override the default
options which include -ansi -pendantic and -Wlong-long... */
extern int printf (const char *, ...);
......
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