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Commit 95385cbb by Aldy Hernandez Committed by Aldy Hernandez
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rs6000.c (altivec_expand_builtin): Add support for mtvscr, dssall, mfvscr, dss,… 

rs6000.c (altivec_expand_builtin): Add support for mtvscr, dssall, mfvscr, dss, lvsl, lvsr, dstt, dst, dstst, dststt.

	* config/rs6000/rs6000.c (altivec_expand_builtin): Add support for
	mtvscr, dssall, mfvscr, dss, lvsl, lvsr, dstt, dst, dstst, dststt.
	(altivec_init_builtins): Same.
	(altivec_expand_unop_builtin): Return NULL_RTX on error.
	(altivec_expand_binop_builtin): Same.
	(altivec_expand_ternop_builtin): Same.
	(bdesc_dst): New.

	* config/rs6000/rs6000.md ("altivec_mtvscr"): New.
	("altivec_vctuxs"): Fix typo.
	("altivec_vnmsubfp"): Same.
	("altivec_dssall"): New.
	("altivec_mfvscr"): New.
	("altivec_dss"): New.
	("altivec_lvsl"): New.
	("altivec_lvsr"): New.
	("altivec_dstt"): New.
	("altivec_dstst"): New.
	("altivec_dststt"): New.
	("altivec_dst"): New.

	* config/rs6000/rs6000.h (rs6000_builtins): Add mtvscr, dssall,
	mfvscr, dss, lvsl, lvsr, dstt, dstst, dststt, dst.

From-SVN: r48708
parent e4ac76b4
Showing with 289 additions and 20 deletions
gcc/ChangeLog
2002-01-08 Aldy Hernandez <aldyh@redhat.com>
* testuite/gcc.dg/altivec-4.c: Add test for mtvscr, dssall,
mfvscr, dss, lvsl, lvsr, dstt, dstst, dststt, dst.
* config/rs6000/rs6000.c (altivec_expand_builtin): Add support for
mtvscr, dssall, mfvscr, dss, lvsl, lvsr, dstt, dst, dstst, dststt.
(altivec_init_builtins): Same.
(altivec_expand_unop_builtin): Return NULL_RTX on error.
(altivec_expand_binop_builtin): Same.
(altivec_expand_ternop_builtin): Same.
(bdesc_dst): New.
* config/rs6000/rs6000.md ("altivec_mtvscr"): New.
("altivec_vctuxs"): Fix typo.
("altivec_vnmsubfp"): Same.
("altivec_dssall"): New.
("altivec_mfvscr"): New.
("altivec_dss"): New.
("altivec_lvsl"): New.
("altivec_lvsr"): New.
("altivec_dstt"): New.
("altivec_dstst"): New.
("altivec_dststt"): New.
("altivec_dst"): New.
* config/rs6000/rs6000.h (rs6000_builtins): Add mtvscr, dssall,
mfvscr, dss, lvsl, lvsr, dstt, dstst, dststt, dst.
2002-01-09 Richard Henderson <rth@redhat.com>
* config/alpha/alpha.md (prologue_mcount): Remove lituse_jsr reloc.
......
gcc/config/rs6000/rs6000.h
......@@ -2967,5 +2967,15 @@ enum rs6000_builtins
ALTIVEC_BUILTIN_VCMPGTSW_P,
ALTIVEC_BUILTIN_VCMPGTUB_P,
ALTIVEC_BUILTIN_VCMPGTUH_P,
ALTIVEC_BUILTIN_VCMPGTUW_P
ALTIVEC_BUILTIN_VCMPGTUW_P,
ALTIVEC_BUILTIN_MTVSCR,
ALTIVEC_BUILTIN_MFVSCR,
ALTIVEC_BUILTIN_DSSALL,
ALTIVEC_BUILTIN_DSS,
ALTIVEC_BUILTIN_LVSL,
ALTIVEC_BUILTIN_LVSR,
ALTIVEC_BUILTIN_DSTT,
ALTIVEC_BUILTIN_DSTST,
ALTIVEC_BUILTIN_DSTSTT,
ALTIVEC_BUILTIN_DST
};
gcc/config/rs6000/rs6000.md
......@@ -14268,7 +14268,7 @@
(match_operand:V4SF 2 "register_operand" "v"))
(match_operand:V4SF 3 "register_operand" "v")))]
"TARGET_ALTIVEC"
"vmmsubfp %0,%1,%2,%3"
"vnmsubfp %0,%1,%2,%3"
[(set_attr "type" "vecfloat")])
......@@ -15142,7 +15142,7 @@
(unspec:V4SI [(match_operand:V4SF 1 "register_operand" "v")
(match_operand:QI 2 "immediate_operand" "i")] 153))]
"TARGET_ALTIVEC"
"vctusx %0, %1, %2"
"vctuxs %0, %1, %2"
[(set_attr "type" "vecfloat")])
(define_insn "altivec_vctsxs"
......@@ -15399,4 +15399,77 @@
(match_operand:V8HI 2 "register_operand" "v")] 185))]
"TARGET_ALTIVEC"
"vcmpgtsh. %0,%1,%2"
[(set_attr "type" "veccmp")])
[(set_attr "type" "veccmp")])
(define_insn "altivec_mtvscr"
[(unspec [(match_operand:V4SI 0 "register_operand" "v")] 186)]
"TARGET_ALTIVEC"
"mtvscr %0"
[(set_attr "type" "vecsimple")])
(define_insn "altivec_mfvscr"
[(set (match_operand:V8HI 0 "register_operand" "=v")
(unspec:V8HI [(const_int 0)] 187))]
"TARGET_ALTIVEC"
"mfvscr %0"
[(set_attr "type" "vecsimple")])
(define_insn "altivec_dssall"
[(unspec [(const_int 0)] 188)]
"TARGET_ALTIVEC"
"dssall"
[(set_attr "type" "vecsimple")])
(define_insn "altivec_dss"
[(unspec [(match_operand:QI 0 "immediate_operand" "i")] 189)]
"TARGET_ALTIVEC"
"dss %0"
[(set_attr "type" "vecsimple")])
(define_insn "altivec_dst"
[(unspec [(match_operand:SI 0 "register_operand" "b")
(match_operand:SI 1 "register_operand" "r")
(match_operand:QI 2 "immediate_operand" "i")] 190)]
"TARGET_ALTIVEC"
"dst %0,%1,%2"
[(set_attr "type" "vecsimple")])
(define_insn "altivec_dstt"
[(unspec [(match_operand:SI 0 "register_operand" "b")
(match_operand:SI 1 "register_operand" "r")
(match_operand:QI 2 "immediate_operand" "i")] 191)]
"TARGET_ALTIVEC"
"dstt %0,%1,%2"
[(set_attr "type" "vecsimple")])
(define_insn "altivec_dstst"
[(unspec [(match_operand:SI 0 "register_operand" "b")
(match_operand:SI 1 "register_operand" "r")
(match_operand:QI 2 "immediate_operand" "i")] 192)]
"TARGET_ALTIVEC"
"dstst %0,%1,%2"
[(set_attr "type" "vecsimple")])
(define_insn "altivec_dststt"
[(unspec [(match_operand:SI 0 "register_operand" "b")
(match_operand:SI 1 "register_operand" "r")
(match_operand:QI 2 "immediate_operand" "i")] 193)]
"TARGET_ALTIVEC"
"dststt %0,%1,%2"
[(set_attr "type" "vecsimple")])
(define_insn "altivec_lvsl"
[(set (match_operand:V16QI 0 "register_operand" "=v")
(unspec:V16QI [(match_operand:SI 1 "register_operand" "r")
(match_operand:SI 2 "register_operand" "r")] 194))]
"TARGET_ALTIVEC"
"lvsl %0,%1,%2"
[(set_attr "type" "vecload")])
(define_insn "altivec_lvsr"
[(set (match_operand:V16QI 0 "register_operand" "=v")
(unspec:V16QI [(match_operand:SI 1 "register_operand" "r")
(match_operand:SI 2 "register_operand" "r")] 195))]
"TARGET_ALTIVEC"
"lvsr %0,%1,%2"
[(set_attr "type" "vecload")])
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