Skip to content

R
riscv-gcc-1
Commit 952ac945 by Carl Love Committed by Carl Love
Options

rs6000-c.c: Add support for built-in functions vector bool char vec_reve (vector bool char)... 

gcc/ChangeLog:

2017-06-26  Carl Love  <cel@us.ibm.com>

	* config/rs6000/rs6000-c.c: Add support for built-in functions
	vector bool char vec_reve (vector bool char);
	vector signed char vec_reve (vector signed char);
	vector unsigned char vec_reve (vector unsigned char);
	vector bool int vec_reve (vector bool int);
	vector signed int vec_reve (vector signed int);
	vector unsigned int vec_reve (vector unsigned int);
	vector bool long long vec_reve (vector bool long long);
	vector signed long long vec_reve (vector signed long long);
	vector unsigned long long vec_reve (vector unsigned long long);
	vector bool short vec_reve (vector bool short);
	vector signed short vec_reve (vector signed short);
	vector double vec_reve (vector double);
	vector float vec_reve (vector float);
	* config/rs6000/rs6000-builtin.def (VREVE_V2DI, VREVE_V4SI,
	VREVE_V8HI, VREVE_V16QI, VREVE_V2DF, VREVE_V4SF, VREVE): New builtin.
	* config/rs6000/altivec.md (UNSPEC_VREVEV): New UNSPEC.
	(altivec_vreve): New pattern.
	* config/rs6000/altivec.h (vec_reve): New define.
	* doc/extend.texi (vec_rev): Update the built-in documentation file
	for the new built-in functions.

gcc/testsuite/ChangeLog:

2017-06-26  Carl Love  <cel@us.ibm.com>

	* gcc.target/powerpc/builtins-3-vec_reve-runnable.c:
	Add new runnable test file for the vec_rev built-ins.

From-SVN: r249650
parent 226ab0a8
Showing with 109 additions and 0 deletions
gcc/ChangeLog
gcc/ChangeLog:
2017-06-26 Carl Love <cel@us.ibm.com>
* config/rs6000/rs6000-c.c: Add support for built-in functions
vector bool char vec_reve (vector bool char);
vector signed char vec_reve (vector signed char);
vector unsigned char vec_reve (vector unsigned char);
vector bool int vec_reve (vector bool int);
vector signed int vec_reve (vector signed int);
vector unsigned int vec_reve (vector unsigned int);
vector bool long long vec_reve (vector bool long long);
vector signed long long vec_reve (vector signed long long);
vector unsigned long long vec_reve (vector unsigned long long);
vector bool short vec_reve (vector bool short);
vector signed short vec_reve (vector signed short);
vector double vec_reve (vector double);
vector float vec_reve (vector float);
* config/rs6000/rs6000-builtin.def (VREVE_V2DI, VREVE_V4SI,
VREVE_V8HI, VREVE_V16QI, VREVE_V2DF, VREVE_V4SF, VREVE): New builtin.
* config/rs6000/altivec.md (UNSPEC_VREVEV): New UNSPEC.
(altivec_vreve): New pattern.
* config/rs6000/altivec.h (vec_reve): New define.
* doc/extend.texi (vec_rev): Update the built-in documentation file
for the new built-in functions.
2016-06-26 Bill Schmidt <wschmidt@linux.vnet.ibm.com>
PR tree-optimization/71815
......
gcc/config/rs6000/altivec.h
......@@ -142,6 +142,7 @@
#define vec_madd __builtin_vec_madd
#define vec_madds __builtin_vec_madds
#define vec_mtvscr __builtin_vec_mtvscr
#define vec_reve __builtin_vec_vreve
#define vec_vmaxfp __builtin_vec_vmaxfp
#define vec_vmaxsw __builtin_vec_vmaxsw
#define vec_vmaxsh __builtin_vec_vmaxsh
......
gcc/config/rs6000/altivec.md
......@@ -50,6 +50,7 @@
UNSPEC_VPACK_UNS_UNS_SAT
UNSPEC_VPACK_UNS_UNS_MOD
UNSPEC_VPACK_UNS_UNS_MOD_DIRECT
UNSPEC_VREVEV
UNSPEC_VSLV4SI
UNSPEC_VSLO
UNSPEC_VSR
......@@ -3820,6 +3821,31 @@
DONE;
}")
;; Vector reverse elements
(define_expand "altivec_vreve<mode>2"
[(set (match_operand:VEC_A 0 "register_operand" "=v")
(unspec:VEC_A [(match_operand:VEC_A 1 "register_operand" "v")]
UNSPEC_VREVEV))]
"TARGET_ALTIVEC"
{
int i, j, size, num_elements;
rtvec v = rtvec_alloc (16);
rtx mask = gen_reg_rtx (V16QImode);
size = GET_MODE_UNIT_SIZE (<MODE>mode);
num_elements = GET_MODE_NUNITS (<MODE>mode);
for (j = 0; j < num_elements; j++)
for (i = 0; i < size; i++)
RTVEC_ELT (v, i + j * size)
= GEN_INT (i + (num_elements - 1 - j) * size);
emit_insn (gen_vec_initv16qi (mask, gen_rtx_PARALLEL (V16QImode, v)));
emit_insn (gen_altivec_vperm_<mode> (operands[0], operands[1],
operands[1], mask));
DONE;
})
;; Vector SIMD PEM v2.06c defines LVLX, LVLXL, LVRX, LVRXL,
;; STVLX, STVLXL, STVVRX, STVRXL are available only on Cell.
(define_insn "altivec_lvlx"
......
gcc/config/rs6000/rs6000-builtin.def
......@@ -1134,6 +1134,13 @@ BU_ALTIVEC_1 (VUPKLSB, "vupklsb", CONST, altivec_vupklsb)
BU_ALTIVEC_1 (VUPKLPX, "vupklpx", CONST, altivec_vupklpx)
BU_ALTIVEC_1 (VUPKLSH, "vupklsh", CONST, altivec_vupklsh)
BU_ALTIVEC_1 (VREVE_V2DI, "vreve_v2di", CONST, altivec_vrevev2di2)
BU_ALTIVEC_1 (VREVE_V4SI, "vreve_v4si", CONST, altivec_vrevev4si2)
BU_ALTIVEC_1 (VREVE_V8HI, "vreve_v8hi", CONST, altivec_vrevev8hi2)
BU_ALTIVEC_1 (VREVE_V16QI, "vreve_v16qi", CONST, altivec_vrevev16qi2)
BU_ALTIVEC_1 (VREVE_V2DF, "vreve_v2df", CONST, altivec_vrevev2df2)
BU_ALTIVEC_1 (VREVE_V4SF, "vreve_v4sf", CONST, altivec_vrevev4sf2)
BU_ALTIVEC_1 (FLOAT_V4SI_V4SF, "float_sisf", FP, floatv4siv4sf2)
BU_ALTIVEC_1 (UNSFLOAT_V4SI_V4SF, "uns_float_sisf", FP, floatunsv4siv4sf2)
BU_ALTIVEC_1 (FIX_V4SF_V4SI, "fix_sfsi", FP, fix_truncv4sfv4si2)
......@@ -1422,6 +1429,8 @@ BU_ALTIVEC_OVERLOAD_1 (VUPKLPX, "vupklpx")
BU_ALTIVEC_OVERLOAD_1 (VUPKLSB, "vupklsb")
BU_ALTIVEC_OVERLOAD_1 (VUPKLSH, "vupklsh")
BU_ALTIVEC_OVERLOAD_1 (VREVE, "vreve")
/* Overloaded altivec predicates. */
BU_ALTIVEC_OVERLOAD_P (VCMPEQ_P, "vcmpeq_p")
BU_ALTIVEC_OVERLOAD_P (VCMPGT_P, "vcmpgt_p")
......
gcc/config/rs6000/rs6000-c.c
......@@ -5521,6 +5521,35 @@ const struct altivec_builtin_types altivec_overloaded_builtins[] = {
{ P9V_BUILTIN_VEC_REVB, P9V_BUILTIN_XXBRH_V8HI,
RS6000_BTI_V8HI, RS6000_BTI_V8HI, 0, 0 },
{ ALTIVEC_BUILTIN_VEC_VREVE, ALTIVEC_BUILTIN_VREVE_V2DI,
RS6000_BTI_V2DI, RS6000_BTI_V2DI, 0, 0 },
{ ALTIVEC_BUILTIN_VEC_VREVE, ALTIVEC_BUILTIN_VREVE_V4SI,
RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0, 0 },
{ ALTIVEC_BUILTIN_VEC_VREVE, ALTIVEC_BUILTIN_VREVE_V8HI,
RS6000_BTI_V8HI, RS6000_BTI_V8HI, 0, 0 },
{ ALTIVEC_BUILTIN_VEC_VREVE, ALTIVEC_BUILTIN_VREVE_V16QI,
RS6000_BTI_V16QI, RS6000_BTI_V16QI, 0, 0 },
{ ALTIVEC_BUILTIN_VEC_VREVE, ALTIVEC_BUILTIN_VREVE_V2DI,
RS6000_BTI_bool_V2DI, RS6000_BTI_bool_V2DI, 0, 0 },
{ ALTIVEC_BUILTIN_VEC_VREVE, ALTIVEC_BUILTIN_VREVE_V4SI,
RS6000_BTI_bool_V4SI, RS6000_BTI_bool_V4SI, 0, 0 },
{ ALTIVEC_BUILTIN_VEC_VREVE, ALTIVEC_BUILTIN_VREVE_V8HI,
RS6000_BTI_bool_V8HI, RS6000_BTI_bool_V8HI, 0, 0 },
{ ALTIVEC_BUILTIN_VEC_VREVE, ALTIVEC_BUILTIN_VREVE_V16QI,
RS6000_BTI_bool_V16QI, RS6000_BTI_bool_V16QI, 0, 0 },
{ ALTIVEC_BUILTIN_VEC_VREVE, ALTIVEC_BUILTIN_VREVE_V2DF,
RS6000_BTI_V2DF, RS6000_BTI_V2DF, 0, 0 },
{ ALTIVEC_BUILTIN_VEC_VREVE, ALTIVEC_BUILTIN_VREVE_V4SF,
RS6000_BTI_V4SF, RS6000_BTI_V4SF, 0, 0 },
{ ALTIVEC_BUILTIN_VEC_VREVE, ALTIVEC_BUILTIN_VREVE_V2DI,
RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, 0, 0 },
{ ALTIVEC_BUILTIN_VEC_VREVE, ALTIVEC_BUILTIN_VREVE_V4SI,
RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, 0, 0 },
{ ALTIVEC_BUILTIN_VEC_VREVE, ALTIVEC_BUILTIN_VREVE_V8HI,
RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, 0, 0 },
{ ALTIVEC_BUILTIN_VEC_VREVE, ALTIVEC_BUILTIN_VREVE_V16QI,
RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, 0, 0 },
/* Crypto builtins. */
{ CRYPTO_BUILTIN_VPERMXOR, CRYPTO_BUILTIN_VPERMXOR_V16QI,
RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI,
......
gcc/doc/extend.texi
......@@ -16558,6 +16558,19 @@ vector bool char vec_perm (vector bool char,
vector float vec_re (vector float);
vector bool char vec_reve (vector bool char);
vector signed char vec_reve (vector signed char);
vector unsigned char vec_reve (vector unsigned char);
vector bool int vec_reve (vector bool int);
vector signed int vec_reve (vector signed int);
vector unsigned int vec_reve (vector unsigned int);
vector bool long long vec_reve (vector bool long long);
vector signed long long vec_reve (vector signed long long);
vector unsigned long long vec_reve (vector unsigned long long);
vector bool short vec_reve (vector bool short);
vector signed short vec_reve (vector signed short);
vector unsigned short vec_reve (vector unsigned short);
vector signed char vec_rl (vector signed char,
vector unsigned char);
vector unsigned char vec_rl (vector unsigned char,
......
gcc/testsuite/ChangeLog
2017-06-26 Carl Love <cel@us.ibm.com>
* gcc.target/powerpc/builtins-3-vec_reve-runnable.c:
Add new runnable test file for the vec_rev built-ins.
2016-06-26 Bill Schmidt <wschmidt@linux.vnet.ibm.com>
PR/tree-optimization 71815
......
Markdown is supported
0% or
You are about to add 0 people to the discussion. Proceed with caution.
Finish editing this message first!
Please register or to comment