Skip to content

R
riscv-gcc-1
Commit 94f7a25e by Wilco Dijkstra Committed by Wilco Dijkstra
Options

Currently the SBFM, UBFM and BFM instructions all use the attribute "bfm". 

SBFM and UBFM include all shifts on AArch64, which are simpler than bitfield
insert.  Add a new bfx attribute for these instructions so that they can be
modelled more accurately in the future.  There is no difference in code 
generation.

	* config/aarch64/aarch64.md (aarch64_ashl_sisd_or_int_<mode>3)
	Use bfx attribute.
	(aarch64_lshr_sisd_or_int_<mode>3): Likewise.
	(aarch64_ashr_sisd_or_int_<mode>3): Likewise.
	(<optab>si3_insn_uxtw): Likewise.
	(<optab><mode>3_insn): Likewise.
	(<ANY_EXTEND:optab><GPI:mode>_ashl<SHORT:mode>): Likewise.
	(zero_extend<GPI:mode>_lshr<SHORT:mode>): Likewise.
	(extend<GPI:mode>_ashr<SHORT:mode>): Likewise.
	(<optab><mode>): Likewise.
	(insv<mode>): Likewise.
	(andim_ashift<mode>_bfiz): Likewise.
	* config/aarch64/thunderx.md (thunderx_shift): Add bfx.
	* config/arm/cortex-a53.md (cortex_a53_alu_shift): Likewise.
	* config/arm/cortex-a57.md (cortex_a57_alu): Add bfx.
	* config/arm/exynos-m1.md (exynos_m1_alu): Add bfx.
	(exynos_m1_alu_p): Likewise.
	* config/arm/types.md: Add bfx.
	* config/arm/xgene1.md (xgene1_bfm): Add bfx.

From-SVN: r242384
parent db4a1c18
Showing with 41 additions and 17 deletions
gcc/ChangeLog
2016-11-14 Wilco Dijkstra <wdijkstr@arm.com>
* config/aarch64/aarch64.md (aarch64_ashl_sisd_or_int_<mode>3)
Use bfx attribute.
(aarch64_lshr_sisd_or_int_<mode>3): Likewise.
(aarch64_ashr_sisd_or_int_<mode>3): Likewise.
(<optab>si3_insn_uxtw): Likewise.
(<optab><mode>3_insn): Likewise.
(<ANY_EXTEND:optab><GPI:mode>_ashl<SHORT:mode>): Likewise.
(zero_extend<GPI:mode>_lshr<SHORT:mode>): Likewise.
(extend<GPI:mode>_ashr<SHORT:mode>): Likewise.
(<optab><mode>): Likewise.
(insv<mode>): Likewise.
(andim_ashift<mode>_bfiz): Likewise.
* config/aarch64/thunderx.md (thunderx_shift): Add bfx.
* config/arm/cortex-a53.md (cortex_a53_alu_shift): Likewise.
* config/arm/cortex-a57.md (cortex_a57_alu): Add bfx.
* config/arm/exynos-m1.md (exynos_m1_alu): Add bfx.
(exynos_m1_alu_p): Likewise.
* config/arm/types.md: Add bfx.
* config/arm/xgene1.md (xgene1_bfm): Add bfx.
2016-11-14 Wilco Dijkstra <wdijkstr@arm.com>
* config/aarch64/aarch64.c (cortexa57_vector_cost):
Change vec_stmt_cost, vec_align_load_cost and vec_unalign_load_cost.
gcc/config/aarch64/aarch64.md
......@@ -3955,7 +3955,7 @@
shl\t%<rtn>0<vas>, %<rtn>1<vas>, %2
ushl\t%<rtn>0<vas>, %<rtn>1<vas>, %<rtn>2<vas>"
[(set_attr "simd" "no,no,yes,yes")
(set_attr "type" "bfm,shift_reg,neon_shift_imm<q>, neon_shift_reg<q>")]
(set_attr "type" "bfx,shift_reg,neon_shift_imm<q>, neon_shift_reg<q>")]
)
;; Logical right shift using SISD or Integer instruction
......@@ -3972,7 +3972,7 @@
#
#"
[(set_attr "simd" "no,no,yes,yes,yes")
(set_attr "type" "bfm,shift_reg,neon_shift_imm<q>,neon_shift_reg<q>,neon_shift_reg<q>")]
(set_attr "type" "bfx,shift_reg,neon_shift_imm<q>,neon_shift_reg<q>,neon_shift_reg<q>")]
)
(define_split
......@@ -4019,7 +4019,7 @@
#
#"
[(set_attr "simd" "no,no,yes,yes,yes")
(set_attr "type" "bfm,shift_reg,neon_shift_imm<q>,neon_shift_reg<q>,neon_shift_reg<q>")]
(set_attr "type" "bfx,shift_reg,neon_shift_imm<q>,neon_shift_reg<q>,neon_shift_reg<q>")]
)
(define_split
......@@ -4129,7 +4129,7 @@
"@
<shift>\\t%w0, %w1, %2
<shift>\\t%w0, %w1, %w2"
[(set_attr "type" "bfm,shift_reg")]
[(set_attr "type" "bfx,shift_reg")]
)
(define_insn "*<optab><mode>3_insn"
......@@ -4141,7 +4141,7 @@
operands[3] = GEN_INT (<sizen> - UINTVAL (operands[2]));
return "<bfshift>\t%w0, %w1, %2, %3";
}
[(set_attr "type" "bfm")]
[(set_attr "type" "bfx")]
)
(define_insn "*extr<mode>5_insn"
......@@ -4234,7 +4234,7 @@
operands[3] = GEN_INT (<SHORT:sizen> - UINTVAL (operands[2]));
return "<su>bfiz\t%<GPI:w>0, %<GPI:w>1, %2, %3";
}
[(set_attr "type" "bfm")]
[(set_attr "type" "bfx")]
)
(define_insn "*zero_extend<GPI:mode>_lshr<SHORT:mode>"
......@@ -4247,7 +4247,7 @@
operands[3] = GEN_INT (<SHORT:sizen> - UINTVAL (operands[2]));
return "ubfx\t%<GPI:w>0, %<GPI:w>1, %2, %3";
}
[(set_attr "type" "bfm")]
[(set_attr "type" "bfx")]
)
(define_insn "*extend<GPI:mode>_ashr<SHORT:mode>"
......@@ -4260,7 +4260,7 @@
operands[3] = GEN_INT (<SHORT:sizen> - UINTVAL (operands[2]));
return "sbfx\\t%<GPI:w>0, %<GPI:w>1, %2, %3";
}
[(set_attr "type" "bfm")]
[(set_attr "type" "bfx")]
)
;; -------------------------------------------------------------------
......@@ -4292,7 +4292,7 @@
"IN_RANGE (INTVAL (operands[2]) + INTVAL (operands[3]),
1, GET_MODE_BITSIZE (<MODE>mode) - 1)"
"<su>bfx\\t%<w>0, %<w>1, %3, %2"
[(set_attr "type" "bfm")]
[(set_attr "type" "bfx")]
)
;; Bitfield Insert (insv)
......@@ -4374,7 +4374,7 @@
: GEN_INT (<GPI:sizen> - UINTVAL (operands[2]));
return "<su>bfiz\t%<GPI:w>0, %<GPI:w>1, %2, %3";
}
[(set_attr "type" "bfm")]
[(set_attr "type" "bfx")]
)
;; XXX We should match (any_extend (ashift)) here, like (and (ashift)) below
......@@ -4386,7 +4386,7 @@
(match_operand 3 "const_int_operand" "n")))]
"aarch64_mask_and_shift_for_ubfiz_p (<MODE>mode, operands[3], operands[2])"
"ubfiz\\t%<w>0, %<w>1, %2, %P3"
[(set_attr "type" "bfm")]
[(set_attr "type" "bfx")]
)
(define_insn "bswap<mode>2"
......
gcc/config/aarch64/thunderx.md
......@@ -39,7 +39,7 @@
(define_insn_reservation "thunderx_shift" 1
(and (eq_attr "tune" "thunderx")
(eq_attr "type" "bfm,extend,rotate_imm,shift_imm,shift_reg,rbit,rev"))
(eq_attr "type" "bfm,bfx,extend,rotate_imm,shift_imm,shift_reg,rbit,rev"))
"thunderx_pipe0 | thunderx_pipe1")
......
gcc/config/arm/cortex-a53.md
......@@ -93,7 +93,7 @@
(and (eq_attr "tune" "cortexa53")
(eq_attr "type" "alu_shift_imm,alus_shift_imm,
crc,logic_shift_imm,logics_shift_imm,
alu_ext,alus_ext,bfm,extend,mvn_shift"))
alu_ext,alus_ext,bfm,bfx,extend,mvn_shift"))
"cortex_a53_slot_any")
(define_insn_reservation "cortex_a53_alu_shift_reg" 3
......
gcc/config/arm/cortex-a57.md
......@@ -297,7 +297,7 @@
(eq_attr "type" "alu_imm,alus_imm,logic_imm,logics_imm,\
alu_sreg,alus_sreg,logic_reg,logics_reg,\
adc_imm,adcs_imm,adc_reg,adcs_reg,\
adr,bfm,clz,csel,rbit,rev,alu_dsp_reg,\
adr,bfm,bfx,clz,rbit,rev,alu_dsp_reg,\
rotate_imm,shift_imm,shift_reg,\
mov_imm,mov_reg,\
mvn_imm,mvn_reg,\
......
gcc/config/arm/exynos-m1.md
......@@ -358,7 +358,7 @@
(eq_attr "type" "alu_imm, alus_imm, logic_imm, logics_imm,\
alu_sreg, alus_sreg, logic_reg, logics_reg,\
adc_imm, adcs_imm, adc_reg, adcs_reg,\
adr, bfm, clz, rbit, rev, csel, alu_dsp_reg,\
adr, bfm, bfx, clz, rbit, rev, csel, alu_dsp_reg,\
shift_imm, shift_reg, rotate_imm, extend,\
mov_imm, mov_reg,\
mvn_imm, mvn_reg,\
......@@ -372,7 +372,7 @@
(eq_attr "type" "alu_imm, alus_imm, logic_imm, logics_imm,\
alu_sreg, alus_sreg, logic_reg, logics_reg,\
adc_imm, adcs_imm, adc_reg, adcs_reg,\
adr, bfm, clz, rbit, rev, alu_dsp_reg,\
adr, bfm, bfx, clz, rbit, rev, alu_dsp_reg,\
shift_imm, shift_reg, rotate_imm, extend,\
mov_imm, mov_reg,\
mvn_imm, mvn_reg,\
......
gcc/config/arm/types.md
......@@ -51,6 +51,7 @@
; alus_shift_imm as alu_shift_imm, setting condition flags.
; alus_shift_reg as alu_shift_reg, setting condition flags.
; bfm bitfield move operation.
; bfx bitfield extract operation.
; block blockage insn, this blocks all functional units.
; branch branch.
; call subroutine call.
......@@ -557,6 +558,7 @@
alus_shift_imm,\
alus_shift_reg,\
bfm,\
bfx,\
block,\
branch,\
call,\
......
gcc/config/arm/xgene1.md
......@@ -164,7 +164,7 @@
(define_insn_reservation "xgene1_bfm" 2
(and (eq_attr "tune" "xgene1")
(eq_attr "type" "bfm"))
(eq_attr "type" "bfm,bfx"))
"xgene1_decode1op,xgene1_fsu")
(define_insn_reservation "xgene1_f_rint" 5
......
Markdown is supported
0% or
You are about to add 0 people to the discussion. Proceed with caution.
Finish editing this message first!
Please register or to comment