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riscv-gcc-1
Commit 9425fb04 by Peter Barada Committed by Bernardo Innocenti
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m68k-none.h: Introduce new ColdFire archs. 

	* config/m68k/m68k-none.h: Introduce new ColdFire archs.
	* config/m68k/m68k.h: Likewise.
	* config/m68k/lb1sf68.asm: Rename __mcf5200__ to __mcoldfire__.
	* config/m68k/coff.h: Rename TARGET_5200 to TARGET_COLDFIRE.
	* config/m68k/linux.h: Likewise.
	* config/m68k/m68k.c: Likewise.
	* config/m68k/m68k.md: Likewise.
	* config/m68k/m68kelf.h: Likewise.
	* config/m68k/netbsd-elf.h: Likewise.
	* config/m68k/t-m68kelf: Add multilib targets for new ColdFire archs.

Co-Authored-By: Bernardo Innocenti <bernie@develer.com>

From-SVN: r70630
parent 03d4ad27
Showing with 115 additions and 49 deletions
gcc/ChangeLog
2003-08-06 Peter Barada <peter@baradas.org>
Bernardo Innocenti <bernie@develer.com>
* config/m68k/m68k-none.h: Introduce new ColdFire archs.
* config/m68k/m68k.h: Likewise.
* config/m68k/lb1sf68.asm: Rename __mcf5200__ to __mcoldfire__.
* config/m68k/coff.h: Rename TARGET_5200 to TARGET_COLDFIRE.
* config/m68k/linux.h: Likewise.
* config/m68k/m68k.c: Likewise.
* config/m68k/m68k.md: Likewise.
* config/m68k/m68kelf.h: Likewise.
* config/m68k/netbsd-elf.h: Likewise.
* config/m68k/t-m68kelf: Add multilib targets for new ColdFire archs.
2003-08-20 Bernardo Innocenti <bernie@develer.com> 2003-08-20 Bernardo Innocenti <bernie@develer.com>
* config/m68k/m68k.c: Strip away code depending on NO_ADDSUB_Q definition. * config/m68k/m68k.c: Strip away code depending on NO_ADDSUB_Q definition.
......
gcc/config/m68k/coff.h
...@@ -57,7 +57,7 @@ Boston, MA 02111-1307, USA. */ ...@@ -57,7 +57,7 @@ Boston, MA 02111-1307, USA. */
#define ASM_RETURN_CASE_JUMP \ #define ASM_RETURN_CASE_JUMP \
do { \ do { \
if (TARGET_5200) \ if (TARGET_COLDFIRE) \
{ \ { \
if (ADDRESS_REG_P (operands[0])) \ if (ADDRESS_REG_P (operands[0])) \
return "jmp %%pc@(2,%0:l)"; \ return "jmp %%pc@(2,%0:l)"; \
......
gcc/config/m68k/linux.h
...@@ -171,7 +171,7 @@ Boston, MA 02111-1307, USA. */ ...@@ -171,7 +171,7 @@ Boston, MA 02111-1307, USA. */
#undef ASM_OUTPUT_CASE_LABEL #undef ASM_OUTPUT_CASE_LABEL
#define ASM_RETURN_CASE_JUMP \ #define ASM_RETURN_CASE_JUMP \
do { \ do { \
if (TARGET_5200) \ if (TARGET_COLDFIRE) \
{ \ { \
if (ADDRESS_REG_P (operands[0])) \ if (ADDRESS_REG_P (operands[0])) \
return "jmp %%pc@(2,%0:l)"; \ return "jmp %%pc@(2,%0:l)"; \
......
gcc/config/m68k/m68k-none.h
...@@ -91,7 +91,7 @@ Unrecognized value in TARGET_CPU_DEFAULT. ...@@ -91,7 +91,7 @@ Unrecognized value in TARGET_CPU_DEFAULT.
#undef CPP_FPU_SPEC #undef CPP_FPU_SPEC
#if TARGET_DEFAULT & MASK_68881 #if TARGET_DEFAULT & MASK_68881
#define CPP_FPU_SPEC "\ #define CPP_FPU_SPEC "\
%{!mc68000:%{!m68000:%{!m68302:%{!mcpu32:%{!m68332:%{!m5200:%{!msoft-float:%{!mno-68881:-D__HAVE_68881__ }}}}}}}} \ %{!mc68000:%{!m68000:%{!m68302:%{!mcpu32:%{!m68332:%{!m5200:%{!m5206e:%{!m528x:%{!m5307:%{!m5407:%{!msoft-float:%{!mno-68881:-D__HAVE_68881__ }}}}}}}}}}}} \
%{m68881:-D__HAVE_68881__ }" %{m68881:-D__HAVE_68881__ }"
#else #else
#define CPP_FPU_SPEC "\ #define CPP_FPU_SPEC "\
...@@ -113,7 +113,12 @@ Unrecognized value in TARGET_CPU_DEFAULT. ...@@ -113,7 +113,12 @@ Unrecognized value in TARGET_CPU_DEFAULT.
-m68302: define mc68302 -m68302: define mc68302
-m68332: define mc68332 mcpu32 -m68332: define mc68332 mcpu32
-mcpu32: define mcpu32 -mcpu32: define mcpu32
-m5200: define mcf5200 -m5200: define mcoldfire mcf5200
-m5206e: define mcoldfire mcf5200 mcf5206e
-m528x: define mcoldfire mc5200 mc528x
-m5307: define mcoldfire mc5300 mc5307
-m5407: define mcoldfire mc5400 mc5407
default: define as above appropriately default: define as above appropriately
GCC won't automatically add __'d versions, we have to mention them GCC won't automatically add __'d versions, we have to mention them
...@@ -121,9 +126,13 @@ Unrecognized value in TARGET_CPU_DEFAULT. ...@@ -121,9 +126,13 @@ Unrecognized value in TARGET_CPU_DEFAULT.
#undef CPP_SPEC #undef CPP_SPEC
#define CPP_SPEC "\ #define CPP_SPEC "\
%(cpp_fpu)%{!ansi:%{m68302:-Dmc68302 }%{m68010:-Dmc68010 }%{m68020:-Dmc68020 }%{mc68020:-Dmc68020 }%{m68030:-Dmc68030 }%{m68040:-Dmc68040 }%{m68020-40:-Dmc68020 -Dmc68030 -Dmc68040 }%{m68020-60:-Dmc68020 -Dmc68030 -Dmc68040 -Dmc68060 }%{m68060:-Dmc68060 }%{mcpu32:-Dmcpu32 } %{m68332:-Dmc68332 -Dmcpu32 }%{m5200:-Dmcf5200 }} \ %(cpp_fpu)%{!ansi:%{m68302:-Dmc68302 }%{m68010:-Dmc68010 }%{m68020:-Dmc68020 }%{mc68020:-Dmc68020 }%{m68030:-Dmc68030 }%{m68040:-Dmc68040 }%{m68020-40:-Dmc68020 -Dmc68030 -Dmc68040 }%{m68020-60:-Dmc68020 -Dmc68030 -Dmc68040 -Dmc68060 }%{m68060:-Dmc68060 }%{mcpu32:-Dmcpu32 } %{m68332:-Dmc68332 -Dmcpu32 }%{m5200:-Dmcoldfire -Dmcf5200 }%{m5206e:-Dmcoldfire -Dmcf5200 -Dmcf5206e }%{m528x:-Dmcoldfire -Dmcf5200 -Dmcf528x }%{m5307:-Dmcoldfire -Dmcf5300 -Dmcf5307 }%{m5407: -Dmcoldfire -Dmcf5400 -Dmcf5407 }} \
%{m68302:-D__mc68302__ -D__mc68302 }%{m68010:-D__mc68010__ -D__mc68010 }%{m68020:-D__mc68020__ -D__mc68020 }%{mc68020:-D__mc68020__ -D__mc68020 }%{m68030:-D__mc68030__ -D__mc68030 }%{m68040:-D__mc68040__ -D__mc68040 }%{m68020-40:-D__mc68020__ -D__mc68030__ -D__mc68040__ -D__mc68020 -D__mc68030 -D__mc68040 }%{m68020-60:-D__mc68020__ -D__mc68030__ -D__mc68040__ -D__mc68020 -D__mc68030 -D__mc68040 -D__mc68060__ -D__mc68060 }%{m68060:-D__mc68060__ -D__mc68060 }%{mcpu32:-D__mcpu32__ -D__mcpu32 }%{m68332:-D__mc68332__ -D__mc68332 -D__mcpu32__ -D__mcpu32 }%{m5200:-D__mcf5200__ -D__mcf5200 } \ %{m68302:-D__mc68302__ -D__mc68302 }%{m68010:-D__mc68010__ -D__mc68010 }%{m68020:-D__mc68020__ -D__mc68020 }%{mc68020:-D__mc68020__ -D__mc68020 }%{m68030:-D__mc68030__ -D__mc68030 }%{m68040:-D__mc68040__ -D__mc68040 }%{m68020-40:-D__mc68020__ -D__mc68030__ -D__mc68040__ -D__mc68020 -D__mc68030 -D__mc68040 }%{m68020-60:-D__mc68020__ -D__mc68030__ -D__mc68040__ -D__mc68020 -D__mc68030 -D__mc68040 -D__mc68060__ -D__mc68060 }%{m68060:-D__mc68060__ -D__mc68060 }%{mcpu32:-D__mcpu32__ -D__mcpu32 }%{m68332:-D__mc68332__ -D__mc68332 -D__mcpu32__ -D__mcpu32 }%{m5200:-D__mcf5200__ -D__mcf5200 -D__mcoldfire__ } \
%{!mc68000:%{!m68000:%{!m68302:%{!m68010:%{!mc68020:%{!m68020:%{!m68030:%{!m68040:%{!m68020-40:%{!m68020-60:%{!m68060:%{!mcpu32: %{!m68332:%{!m5200:%(cpp_cpu_default)}}}}}}}}}}}}}} \ %{m5206e:-D__mcoldfire__ -D__mcf5200__ -D__mcf5200 -D__mcf5206e__ -D__mcf5206e } \
%{m528x:-D__mcoldfire__ -D__mcf5200__ -D__mcf5200 -D__mcf528x__ -D__mcf528x } \
%{m5307:-D__mcoldfire__ -D__mcf5300__ -D__mcf5300 -D__mcf5307__ -D__mcf5307 } \
%{m5407:-D__mcoldfire__ -D__mcf5400__ -D__mcf5400 -D__mcf5407__ -D__mcf5407 } \
%{!mc68000:%{!m68000:%{!m68302:%{!m68010:%{!mc68020:%{!m68020:%{!m68030:%{!m68040:%{!m68020-40:%{!m68020-60:%{!m68060:%{!mcpu32: %{!m68332:%{!m5200:%{!m5206e:%{!m528x:%{!m5307:%{!m5407:%(cpp_cpu_default)}}}}}}}}}}}}}}}}}} \
%(cpp_subtarget) \ %(cpp_subtarget) \
" "
...@@ -131,7 +140,7 @@ Unrecognized value in TARGET_CPU_DEFAULT. ...@@ -131,7 +140,7 @@ Unrecognized value in TARGET_CPU_DEFAULT.
#undef ASM_SPEC #undef ASM_SPEC
#define ASM_SPEC "\ #define ASM_SPEC "\
%{m68851}%{mno-68851}%{m68881}%{mno-68881}%{msoft-float:-mno-68881} %{m68000}%{m68302}%{mc68000}%{m68010}%{m68020}%{mc68020}%{m68030}%{m68040}%{m68020-40:-mc68040} %{m68020-60:-mc68040} %{m68060}%{mcpu32}%{m68332}%{m5200}%{!mc68000:%{!m68000:%{!m68302:%{!m68010:%{!mc68020:%{!m68020:%{!m68030:%{!m68040:%{!m68020-40:%{!m68020-60:%{!m68060:%{!mcpu32:%{!m68332:%{!m5200:%(asm_cpu_default)}}}}}}}}}}}}}} \ %{m68851}%{mno-68851}%{m68881}%{mno-68881}%{msoft-float:-mno-68881} %{m68000}%{m68302}%{mc68000}%{m68010}%{m68020}%{mc68020}%{m68030}%{m68040}%{m68020-40:-mc68040} %{m68020-60:-mc68040} %{m68060}%{mcpu32}%{m68332}%{m5200}%{m5206e}%{m528x}%{m5307}%{m5407}%{!mc68000:%{!m68000:%{!m68302:%{!m68010:%{!mc68020:%{!m68020:%{!m68030:%{!m68040:%{!m68020-40:%{!m68020-60:%{!m68060:%{!mcpu32:%{!m68332:%{!m5200:%{!m5206e:%{!m528x:%{!m5307:%{!m5407:%(asm_cpu_default)}}}}}}}}}}}}}}}}}} \
" "
/* cc1/cc1plus always receives all the -m flags. If the specs strings above /* cc1/cc1plus always receives all the -m flags. If the specs strings above
......
gcc/config/m68k/m68k.c
...@@ -347,7 +347,7 @@ m68k_output_function_prologue (stream, size) ...@@ -347,7 +347,7 @@ m68k_output_function_prologue (stream, size)
{ {
if (fsize + 4 <= 8) if (fsize + 4 <= 8)
{ {
if (!TARGET_5200) if (!TARGET_COLDFIRE)
{ {
/* asm_fprintf() cannot handle %. */ /* asm_fprintf() cannot handle %. */
#ifdef MOTOROLA #ifdef MOTOROLA
...@@ -511,7 +511,7 @@ m68k_output_function_prologue (stream, size) ...@@ -511,7 +511,7 @@ m68k_output_function_prologue (stream, size)
} }
else if (mask) else if (mask)
{ {
if (TARGET_5200) if (TARGET_COLDFIRE)
{ {
/* The coldfire does not support the predecrement form of the /* The coldfire does not support the predecrement form of the
movml instruction, so we must adjust the stack pointer and movml instruction, so we must adjust the stack pointer and
...@@ -666,7 +666,7 @@ m68k_output_function_epilogue (stream, size) ...@@ -666,7 +666,7 @@ m68k_output_function_epilogue (stream, size)
#endif #endif
fsize = 0, big = 1; fsize = 0, big = 1;
} }
if (TARGET_5200 || nregs <= 2) if (TARGET_COLDFIRE || nregs <= 2)
{ {
/* Restore each separately in the same order moveml does. /* Restore each separately in the same order moveml does.
Using two movel instructions instead of a single moveml Using two movel instructions instead of a single moveml
...@@ -799,7 +799,7 @@ m68k_output_function_epilogue (stream, size) ...@@ -799,7 +799,7 @@ m68k_output_function_epilogue (stream, size)
{ {
if (fsize + 4 <= 8) if (fsize + 4 <= 8)
{ {
if (!TARGET_5200) if (!TARGET_COLDFIRE)
{ {
#ifdef MOTOROLA #ifdef MOTOROLA
asm_fprintf (stream, "\taddq.w %I%wd,%Rsp\n", fsize + 4); asm_fprintf (stream, "\taddq.w %I%wd,%Rsp\n", fsize + 4);
...@@ -1091,7 +1091,7 @@ output_scc_di(op, operand1, operand2, dest) ...@@ -1091,7 +1091,7 @@ output_scc_di(op, operand1, operand2, dest)
} }
else else
{ {
if (TARGET_68020 || TARGET_5200 || ! ADDRESS_REG_P (loperands[0])) if (TARGET_68020 || TARGET_COLDFIRE || ! ADDRESS_REG_P (loperands[0]))
output_asm_insn ("tst%.l %0", loperands); output_asm_insn ("tst%.l %0", loperands);
else else
{ {
...@@ -1108,7 +1108,7 @@ output_scc_di(op, operand1, operand2, dest) ...@@ -1108,7 +1108,7 @@ output_scc_di(op, operand1, operand2, dest)
output_asm_insn ("jne %l4", loperands); output_asm_insn ("jne %l4", loperands);
#endif #endif
if (TARGET_68020 || TARGET_5200 || ! ADDRESS_REG_P (loperands[1])) if (TARGET_68020 || TARGET_COLDFIRE || ! ADDRESS_REG_P (loperands[1]))
output_asm_insn ("tst%.l %1", loperands); output_asm_insn ("tst%.l %1", loperands);
else else
{ {
...@@ -1426,7 +1426,7 @@ const_method (constant) ...@@ -1426,7 +1426,7 @@ const_method (constant)
/* The Coldfire doesn't have byte or word operations. */ /* The Coldfire doesn't have byte or word operations. */
/* FIXME: This may not be useful for the m68060 either */ /* FIXME: This may not be useful for the m68060 either */
if (!TARGET_5200) if (!TARGET_COLDFIRE)
{ {
/* if -256 < N < 256 but N is not in range for a moveq /* if -256 < N < 256 but N is not in range for a moveq
N^ff will be, so use moveq #N^ff, dreg; not.b dreg. */ N^ff will be, so use moveq #N^ff, dreg; not.b dreg. */
...@@ -1630,7 +1630,7 @@ output_move_simode_const (operands) ...@@ -1630,7 +1630,7 @@ output_move_simode_const (operands)
|| GET_CODE (operands[0]) == MEM) || GET_CODE (operands[0]) == MEM)
/* clr insns on 68000 read before writing. /* clr insns on 68000 read before writing.
This isn't so on the 68010, but we have no TARGET_68010. */ This isn't so on the 68010, but we have no TARGET_68010. */
&& ((TARGET_68020 || TARGET_5200) && ((TARGET_68020 || TARGET_COLDFIRE)
|| !(GET_CODE (operands[0]) == MEM || !(GET_CODE (operands[0]) == MEM
&& MEM_VOLATILE_P (operands[0])))) && MEM_VOLATILE_P (operands[0]))))
return "clr%.l %0"; return "clr%.l %0";
...@@ -1680,7 +1680,7 @@ output_move_himode (operands) ...@@ -1680,7 +1680,7 @@ output_move_himode (operands)
|| GET_CODE (operands[0]) == MEM) || GET_CODE (operands[0]) == MEM)
/* clr insns on 68000 read before writing. /* clr insns on 68000 read before writing.
This isn't so on the 68010, but we have no TARGET_68010. */ This isn't so on the 68010, but we have no TARGET_68010. */
&& ((TARGET_68020 || TARGET_5200) && ((TARGET_68020 || TARGET_COLDFIRE)
|| !(GET_CODE (operands[0]) == MEM || !(GET_CODE (operands[0]) == MEM
&& MEM_VOLATILE_P (operands[0])))) && MEM_VOLATILE_P (operands[0]))))
return "clr%.w %0"; return "clr%.w %0";
...@@ -1746,7 +1746,7 @@ output_move_qimode (operands) ...@@ -1746,7 +1746,7 @@ output_move_qimode (operands)
&& GET_CODE (XEXP (operands[0], 0)) == PRE_DEC && GET_CODE (XEXP (operands[0], 0)) == PRE_DEC
&& XEXP (XEXP (operands[0], 0), 0) == stack_pointer_rtx && XEXP (XEXP (operands[0], 0), 0) == stack_pointer_rtx
&& ! ADDRESS_REG_P (operands[1]) && ! ADDRESS_REG_P (operands[1])
&& ! TARGET_5200) && ! TARGET_COLDFIRE)
{ {
xoperands[1] = operands[1]; xoperands[1] = operands[1];
xoperands[2] xoperands[2]
...@@ -1767,12 +1767,12 @@ output_move_qimode (operands) ...@@ -1767,12 +1767,12 @@ output_move_qimode (operands)
/* clr and st insns on 68000 read before writing. /* clr and st insns on 68000 read before writing.
This isn't so on the 68010, but we have no TARGET_68010. */ This isn't so on the 68010, but we have no TARGET_68010. */
if (!ADDRESS_REG_P (operands[0]) if (!ADDRESS_REG_P (operands[0])
&& ((TARGET_68020 || TARGET_5200) && ((TARGET_68020 || TARGET_COLDFIRE)
|| !(GET_CODE (operands[0]) == MEM && MEM_VOLATILE_P (operands[0])))) || !(GET_CODE (operands[0]) == MEM && MEM_VOLATILE_P (operands[0]))))
{ {
if (operands[1] == const0_rtx) if (operands[1] == const0_rtx)
return "clr%.b %0"; return "clr%.b %0";
if ((!TARGET_5200 || DATA_REG_P (operands[0])) if ((!TARGET_COLDFIRE || DATA_REG_P (operands[0]))
&& GET_CODE (operands[1]) == CONST_INT && GET_CODE (operands[1]) == CONST_INT
&& (INTVAL (operands[1]) & 255) == 255) && (INTVAL (operands[1]) & 255) == 255)
{ {
...@@ -1805,7 +1805,7 @@ output_move_stricthi (operands) ...@@ -1805,7 +1805,7 @@ output_move_stricthi (operands)
if (operands[1] == const0_rtx if (operands[1] == const0_rtx
/* clr insns on 68000 read before writing. /* clr insns on 68000 read before writing.
This isn't so on the 68010, but we have no TARGET_68010. */ This isn't so on the 68010, but we have no TARGET_68010. */
&& ((TARGET_68020 || TARGET_5200) && ((TARGET_68020 || TARGET_COLDFIRE)
|| !(GET_CODE (operands[0]) == MEM && MEM_VOLATILE_P (operands[0])))) || !(GET_CODE (operands[0]) == MEM && MEM_VOLATILE_P (operands[0]))))
return "clr%.w %0"; return "clr%.w %0";
return "move%.w %1,%0"; return "move%.w %1,%0";
...@@ -1818,7 +1818,7 @@ output_move_strictqi (operands) ...@@ -1818,7 +1818,7 @@ output_move_strictqi (operands)
if (operands[1] == const0_rtx if (operands[1] == const0_rtx
/* clr insns on 68000 read before writing. /* clr insns on 68000 read before writing.
This isn't so on the 68010, but we have no TARGET_68010. */ This isn't so on the 68010, but we have no TARGET_68010. */
&& ((TARGET_68020 || TARGET_5200) && ((TARGET_68020 || TARGET_COLDFIRE)
|| !(GET_CODE (operands[0]) == MEM && MEM_VOLATILE_P (operands[0])))) || !(GET_CODE (operands[0]) == MEM && MEM_VOLATILE_P (operands[0]))))
return "clr%.b %0"; return "clr%.b %0";
return "move%.b %1,%0"; return "move%.b %1,%0";
...@@ -3303,7 +3303,7 @@ output_andsi3 (operands) ...@@ -3303,7 +3303,7 @@ output_andsi3 (operands)
&& (INTVAL (operands[2]) | 0xffff) == 0xffffffff && (INTVAL (operands[2]) | 0xffff) == 0xffffffff
&& (DATA_REG_P (operands[0]) && (DATA_REG_P (operands[0])
|| offsettable_memref_p (operands[0])) || offsettable_memref_p (operands[0]))
&& !TARGET_5200) && !TARGET_COLDFIRE)
{ {
if (GET_CODE (operands[0]) != REG) if (GET_CODE (operands[0]) != REG)
operands[0] = adjust_address (operands[0], HImode, 2); operands[0] = adjust_address (operands[0], HImode, 2);
...@@ -3344,7 +3344,7 @@ output_iorsi3 (operands) ...@@ -3344,7 +3344,7 @@ output_iorsi3 (operands)
&& INTVAL (operands[2]) >> 16 == 0 && INTVAL (operands[2]) >> 16 == 0
&& (DATA_REG_P (operands[0]) && (DATA_REG_P (operands[0])
|| offsettable_memref_p (operands[0])) || offsettable_memref_p (operands[0]))
&& !TARGET_5200) && !TARGET_COLDFIRE)
{ {
if (GET_CODE (operands[0]) != REG) if (GET_CODE (operands[0]) != REG)
operands[0] = adjust_address (operands[0], HImode, 2); operands[0] = adjust_address (operands[0], HImode, 2);
...@@ -3380,7 +3380,7 @@ output_xorsi3 (operands) ...@@ -3380,7 +3380,7 @@ output_xorsi3 (operands)
if (GET_CODE (operands[2]) == CONST_INT if (GET_CODE (operands[2]) == CONST_INT
&& INTVAL (operands[2]) >> 16 == 0 && INTVAL (operands[2]) >> 16 == 0
&& (offsettable_memref_p (operands[0]) || DATA_REG_P (operands[0])) && (offsettable_memref_p (operands[0]) || DATA_REG_P (operands[0]))
&& !TARGET_5200) && !TARGET_COLDFIRE)
{ {
if (! DATA_REG_P (operands[0])) if (! DATA_REG_P (operands[0]))
operands[0] = adjust_address (operands[0], HImode, 2); operands[0] = adjust_address (operands[0], HImode, 2);
......
gcc/config/m68k/m68k.h
...@@ -143,6 +143,30 @@ extern int target_flags; ...@@ -143,6 +143,30 @@ extern int target_flags;
#define MASK_NO_STRICT_ALIGNMENT 16384 #define MASK_NO_STRICT_ALIGNMENT 16384
#define TARGET_STRICT_ALIGNMENT (~target_flags & MASK_NO_STRICT_ALIGNMENT) #define TARGET_STRICT_ALIGNMENT (~target_flags & MASK_NO_STRICT_ALIGNMENT)
/* Build for ColdFire v3 */
#define MASK_CFV3 0x8000
#define TARGET_CFV3 (target_flags & MASK_CFV3)
/* Build for ColdFire v4 */
#define MASK_CFV4 0x10000
#define TARGET_CFV4 (target_flags & MASK_CFV4)
/* Divide support for ColdFire */
#define MASK_CF_HWDIV 0x40000
#define TARGET_CF_HWDIV (target_flags & MASK_CF_HWDIV)
/* Compile for mcf582 */
#define MASK_528x 0x80000
#define TARGET_528x (target_flags & MASK_528x)
/* Is the target a coldfire */
#define MASK_COLDFIRE (MASK_5200|MASK_528x|MASK_CFV3|MASK_CFV4)
#define TARGET_COLDFIRE (target_flags & MASK_COLDFIRE)
/* Which bits can be set by specifying a coldfire */
#define MASK_ALL_CF_BITS (MASK_COLDFIRE|MASK_CF_HWDIV)
/* Macro to define tables used to set the flags. /* Macro to define tables used to set the flags.
This is a list in braces of pairs in braces, This is a list in braces of pairs in braces,
each pair being { "NAME", VALUE } each pair being { "NAME", VALUE }
...@@ -150,16 +174,16 @@ extern int target_flags; ...@@ -150,16 +174,16 @@ extern int target_flags;
An empty string NAME is used to identify the default VALUE. */ An empty string NAME is used to identify the default VALUE. */
#define TARGET_SWITCHES \ #define TARGET_SWITCHES \
{ { "68020", - (MASK_5200|MASK_68060|MASK_68040|MASK_68040_ONLY), \ { { "68020", - (MASK_ALL_CF_BITS|MASK_68060|MASK_68040|MASK_68040_ONLY), \
N_("Generate code for a 68020") }, \ N_("Generate code for a 68020") }, \
{ "c68020", - (MASK_5200|MASK_68060|MASK_68040|MASK_68040_ONLY), \ { "c68020", - (MASK_ALL_CF_BITS|MASK_68060|MASK_68040|MASK_68040_ONLY), \
N_("Generate code for a 68020") }, \ N_("Generate code for a 68020") }, \
{ "68020", (MASK_68020|MASK_BITFIELD), "" }, \ { "68020", (MASK_68020|MASK_BITFIELD), "" }, \
{ "c68020", (MASK_68020|MASK_BITFIELD), "" }, \ { "c68020", (MASK_68020|MASK_BITFIELD), "" }, \
{ "68000", - (MASK_5200|MASK_68060|MASK_68040|MASK_68040_ONLY \ { "68000", - (MASK_ALL_CF_BITS|MASK_68060|MASK_68040|MASK_68040_ONLY \
|MASK_68020|MASK_BITFIELD|MASK_68881), \ |MASK_68020|MASK_BITFIELD|MASK_68881), \
N_("Generate code for a 68000") }, \ N_("Generate code for a 68000") }, \
{ "c68000", - (MASK_5200|MASK_68060|MASK_68040|MASK_68040_ONLY \ { "c68000", - (MASK_ALL_CF_BITS|MASK_68060|MASK_68040|MASK_68040_ONLY \
|MASK_68020|MASK_BITFIELD|MASK_68881), \ |MASK_68020|MASK_BITFIELD|MASK_68881), \
N_("Generate code for a 68000") }, \ N_("Generate code for a 68000") }, \
{ "bitfield", MASK_BITFIELD, \ { "bitfield", MASK_BITFIELD, \
...@@ -177,40 +201,56 @@ extern int target_flags; ...@@ -177,40 +201,56 @@ extern int target_flags;
{ "68881", MASK_68881, "" }, \ { "68881", MASK_68881, "" }, \
{ "soft-float", - (MASK_68040_ONLY|MASK_68881), \ { "soft-float", - (MASK_68040_ONLY|MASK_68881), \
N_("Generate code with library calls for floating point") }, \ N_("Generate code with library calls for floating point") }, \
{ "68020-40", -(MASK_5200|MASK_68060|MASK_68040_ONLY), \ { "68020-40", -(MASK_ALL_CF_BITS|MASK_68060|MASK_68040_ONLY), \
N_("Generate code for a 68040, without any new instructions") }, \ N_("Generate code for a 68040, without any new instructions") }, \
{ "68020-40", (MASK_BITFIELD|MASK_68881|MASK_68020|MASK_68040), ""},\ { "68020-40", (MASK_BITFIELD|MASK_68881|MASK_68020|MASK_68040), ""},\
{ "68020-60", -(MASK_5200|MASK_68040_ONLY), \ { "68020-60", -(MASK_ALL_CF_BITS|MASK_68040_ONLY), \
N_("Generate code for a 68060, without any new instructions") }, \ N_("Generate code for a 68060, without any new instructions") }, \
{ "68020-60", (MASK_BITFIELD|MASK_68881|MASK_68020|MASK_68040 \ { "68020-60", (MASK_BITFIELD|MASK_68881|MASK_68020|MASK_68040 \
|MASK_68060), "" }, \ |MASK_68060), "" }, \
{ "68030", - (MASK_5200|MASK_68060|MASK_68040|MASK_68040_ONLY), \ { "68030", - (MASK_ALL_CF_BITS|MASK_68060|MASK_68040|MASK_68040_ONLY), \
N_("Generate code for a 68030") }, \ N_("Generate code for a 68030") }, \
{ "68030", (MASK_68020|MASK_BITFIELD), "" }, \ { "68030", (MASK_68020|MASK_BITFIELD), "" }, \
{ "68040", - (MASK_5200|MASK_68060), \ { "68040", - (MASK_ALL_CF_BITS|MASK_68060), \
N_("Generate code for a 68040") }, \ N_("Generate code for a 68040") }, \
{ "68040", (MASK_68020|MASK_68881|MASK_BITFIELD \ { "68040", (MASK_68020|MASK_68881|MASK_BITFIELD \
|MASK_68040_ONLY|MASK_68040), "" }, \ |MASK_68040_ONLY|MASK_68040), "" }, \
{ "68060", - (MASK_5200|MASK_68040), \ { "68060", - (MASK_ALL_CF_BITS|MASK_68040), \
N_("Generate code for a 68060") }, \ N_("Generate code for a 68060") }, \
{ "68060", (MASK_68020|MASK_68881|MASK_BITFIELD \ { "68060", (MASK_68020|MASK_68881|MASK_BITFIELD \
|MASK_68040_ONLY|MASK_68060), "" }, \ |MASK_68040_ONLY|MASK_68060), "" }, \
{ "5200", - (MASK_68060|MASK_68040|MASK_68040_ONLY|MASK_68020 \ { "5200", - (MASK_ALL_CF_BITS|MASK_68060|MASK_68040|MASK_68040_ONLY|MASK_68020 \
|MASK_BITFIELD|MASK_68881), \ |MASK_BITFIELD|MASK_68881), \
N_("Generate code for a 520X") }, \ N_("Generate code for a 520X") }, \
{ "5200", (MASK_5200), "" }, \ { "5200", (MASK_5200), "" }, \
{ "5206e", - (MASK_ALL_CF_BITS|MASK_68060|MASK_68040|MASK_68040_ONLY|MASK_68020 \
|MASK_BITFIELD|MASK_68881), \
N_("Generate code for a 5206e") }, \
{ "5206e", (MASK_5200|MASK_CF_HWDIV), "" }, \
{ "528x", - (MASK_ALL_CF_BITS|MASK_68060|MASK_68040|MASK_68040_ONLY|MASK_68020 \
|MASK_BITFIELD|MASK_68881), \
N_("Generate code for a 528x") }, \
{ "528x", (MASK_528x|MASK_CF_HWDIV), "" }, \
{ "5307", - (MASK_ALL_CF_BITS|MASK_68060|MASK_68040|MASK_68040_ONLY|MASK_68020 \
|MASK_BITFIELD|MASK_68881), \
N_("Generate code for a 5307") }, \
{ "5307", (MASK_CFV3|MASK_CF_HWDIV), "" }, \
{ "5407", - (MASK_ALL_CF_BITS|MASK_68060|MASK_68040|MASK_68040_ONLY|MASK_68020 \
|MASK_BITFIELD|MASK_68881), \
N_("Generate code for a 5407") }, \
{ "5407", (MASK_CFV4|MASK_CF_HWDIV), "" }, \
{ "68851", 0, \ { "68851", 0, \
N_("Generate code for a 68851") }, \ N_("Generate code for a 68851") }, \
{ "no-68851", 0, \ { "no-68851", 0, \
N_("Do no generate code for a 68851") }, \ N_("Do no generate code for a 68851") }, \
{ "68302", - (MASK_5200|MASK_68060|MASK_68040|MASK_68040_ONLY \ { "68302", - (MASK_ALL_CF_BITS|MASK_68060|MASK_68040|MASK_68040_ONLY \
|MASK_68020|MASK_BITFIELD|MASK_68881), \ |MASK_68020|MASK_BITFIELD|MASK_68881), \
N_("Generate code for a 68302") }, \ N_("Generate code for a 68302") }, \
{ "68332", - (MASK_5200|MASK_68060|MASK_68040|MASK_68040_ONLY \ { "68332", - (MASK_ALL_CF_BITS|MASK_68060|MASK_68040|MASK_68040_ONLY \
|MASK_BITFIELD|MASK_68881), \ |MASK_BITFIELD|MASK_68881), \
N_("Generate code for a 68332") }, \ N_("Generate code for a 68332") }, \
{ "68332", MASK_68020, "" }, \ { "68332", MASK_68020, "" }, \
{ "cpu32", - (MASK_5200|MASK_68060|MASK_68040|MASK_68040_ONLY \ { "cpu32", - (MASK_ALL_CF_BITS|MASK_68060|MASK_68040|MASK_68040_ONLY \
|MASK_BITFIELD|MASK_68881), \ |MASK_BITFIELD|MASK_68881), \
N_("Generate code for a cpu32") }, \ N_("Generate code for a cpu32") }, \
{ "cpu32", MASK_68020, "" }, \ { "cpu32", MASK_68020, "" }, \
...@@ -688,12 +728,12 @@ enum reg_class { ...@@ -688,12 +728,12 @@ enum reg_class {
this says how many the stack pointer really advances by. this says how many the stack pointer really advances by.
On the 68000, sp@- in a byte insn really pushes a word. On the 68000, sp@- in a byte insn really pushes a word.
On the 5200 (coldfire), sp@- in a byte insn pushes just a byte. */ On the 5200 (coldfire), sp@- in a byte insn pushes just a byte. */
#define PUSH_ROUNDING(BYTES) (TARGET_5200 ? BYTES : ((BYTES) + 1) & ~1) #define PUSH_ROUNDING(BYTES) (TARGET_COLDFIRE ? BYTES : ((BYTES) + 1) & ~1)
/* We want to avoid trying to push bytes. */ /* We want to avoid trying to push bytes. */
#define MOVE_BY_PIECES_P(SIZE, ALIGN) \ #define MOVE_BY_PIECES_P(SIZE, ALIGN) \
(move_by_pieces_ninsns (SIZE, ALIGN) < MOVE_RATIO \ (move_by_pieces_ninsns (SIZE, ALIGN) < MOVE_RATIO \
&& (((SIZE) >=16 && (ALIGN) >= 16) || (TARGET_5200))) && (((SIZE) >=16 && (ALIGN) >= 16) || (TARGET_COLDFIRE)))
/* Offset of first parameter from the argument pointer register value. */ /* Offset of first parameter from the argument pointer register value. */
#define FIRST_PARM_OFFSET(FNDECL) 8 #define FIRST_PARM_OFFSET(FNDECL) 8
...@@ -1122,7 +1162,7 @@ __transfer_from_trampoline () \ ...@@ -1122,7 +1162,7 @@ __transfer_from_trampoline () \
/* coldfire/5200 does not allow HImode index registers. */ /* coldfire/5200 does not allow HImode index registers. */
#define LEGITIMATE_INDEX_REG_P(X) \ #define LEGITIMATE_INDEX_REG_P(X) \
((GET_CODE (X) == REG && REG_OK_FOR_INDEX_P (X)) \ ((GET_CODE (X) == REG && REG_OK_FOR_INDEX_P (X)) \
|| (! TARGET_5200 \ || (! TARGET_COLDFIRE \
&& GET_CODE (X) == SIGN_EXTEND \ && GET_CODE (X) == SIGN_EXTEND \
&& GET_CODE (XEXP (X, 0)) == REG \ && GET_CODE (XEXP (X, 0)) == REG \
&& GET_MODE (XEXP (X, 0)) == HImode \ && GET_MODE (XEXP (X, 0)) == HImode \
...@@ -1133,12 +1173,12 @@ __transfer_from_trampoline () \ ...@@ -1133,12 +1173,12 @@ __transfer_from_trampoline () \
#define LEGITIMATE_INDEX_P(X) \ #define LEGITIMATE_INDEX_P(X) \
(LEGITIMATE_INDEX_REG_P (X) \ (LEGITIMATE_INDEX_REG_P (X) \
|| ((TARGET_68020 || TARGET_5200) && GET_CODE (X) == MULT \ || ((TARGET_68020 || TARGET_COLDFIRE) && GET_CODE (X) == MULT \
&& LEGITIMATE_INDEX_REG_P (XEXP (X, 0)) \ && LEGITIMATE_INDEX_REG_P (XEXP (X, 0)) \
&& GET_CODE (XEXP (X, 1)) == CONST_INT \ && GET_CODE (XEXP (X, 1)) == CONST_INT \
&& (INTVAL (XEXP (X, 1)) == 2 \ && (INTVAL (XEXP (X, 1)) == 2 \
|| INTVAL (XEXP (X, 1)) == 4 \ || INTVAL (XEXP (X, 1)) == 4 \
|| (INTVAL (XEXP (X, 1)) == 8 && !TARGET_5200)))) || (INTVAL (XEXP (X, 1)) == 8 && !TARGET_COLDFIRE))))
/* If pic, we accept INDEX+LABEL, which is what do_tablejump makes. */ /* If pic, we accept INDEX+LABEL, which is what do_tablejump makes. */
#define GO_IF_LEGITIMATE_ADDRESS(MODE, X, ADDR) \ #define GO_IF_LEGITIMATE_ADDRESS(MODE, X, ADDR) \
......
gcc/config/m68k/m68kelf.h
...@@ -75,7 +75,7 @@ Boston, MA 02111-1307, USA. */ ...@@ -75,7 +75,7 @@ Boston, MA 02111-1307, USA. */
#define ASM_RETURN_CASE_JUMP \ #define ASM_RETURN_CASE_JUMP \
do { \ do { \
if (TARGET_5200) \ if (TARGET_COLDFIRE) \
{ \ { \
if (ADDRESS_REG_P (operands[0])) \ if (ADDRESS_REG_P (operands[0])) \
return "jmp %%pc@(2,%0:l)"; \ return "jmp %%pc@(2,%0:l)"; \
......
gcc/config/m68k/netbsd-elf.h
...@@ -204,7 +204,7 @@ while (0) ...@@ -204,7 +204,7 @@ while (0)
#undef ASM_OUTPUT_CASE_LABEL #undef ASM_OUTPUT_CASE_LABEL
#define ASM_RETURN_CASE_JUMP \ #define ASM_RETURN_CASE_JUMP \
do { \ do { \
if (TARGET_5200) \ if (TARGET_COLDFIRE) \
{ \ { \
if (ADDRESS_REG_P (operands[0])) \ if (ADDRESS_REG_P (operands[0])) \
return "jmp %%pc@(2,%0:l)"; \ return "jmp %%pc@(2,%0:l)"; \
......
gcc/config/m68k/t-m68kelf
...@@ -12,11 +12,14 @@ xfgnulib.c: $(srcdir)/config/m68k/fpgnulib.c ...@@ -12,11 +12,14 @@ xfgnulib.c: $(srcdir)/config/m68k/fpgnulib.c
echo '#define EXTFLOAT' > xfgnulib.c echo '#define EXTFLOAT' > xfgnulib.c
cat $(srcdir)/config/m68k/fpgnulib.c >> xfgnulib.c cat $(srcdir)/config/m68k/fpgnulib.c >> xfgnulib.c
MULTILIB_OPTIONS = m68000/m68020/m5200/mcpu32/m68040/m68060 m68881/msoft-float MULTILIB_OPTIONS = m68000/m68020/m5200/m5206e/m528x/m5307/m5407/mcpu32/m68040/m68060 m68881/msoft-float
MULTILIB_DIRNAMES = MULTILIB_DIRNAMES =
MULTILIB_MATCHES = m68000=mc68000 m68000=m68302 mcpu32=m68332 m68020=mc68020 MULTILIB_MATCHES = m68000=mc68000 m68000=m68302 mcpu32=m68332 m68020=mc68020 m5206e=m5272
MULTILIB_EXCEPTIONS = m68000/msoft-float m5200/m68881 m5200/msoft-float mcpu32/m68881 mcpu32/msoft-float m68040/m68881 m68040/msoft-float m68060/m68881 m68060/msoft-float MULTILIB_EXCEPTIONS = m68000/msoft-float m5200/m68881 m5200/msoft-float \
m5206e/m68881 m5206e/msoft-float m528x/m68881 m528x/msoft-float \
m5307/m68881 m5307/msoft-float m5407/m68881 m5407/msoft-float \
mcpu32/m68881 mcpu32/msoft-float m68040/m68881 m68040/msoft-float \
m68060/m68881 m68060/msoft-float
LIBGCC = stmp-multilib LIBGCC = stmp-multilib
INSTALL_LIBGCC = install-multilib INSTALL_LIBGCC = install-multilib
......
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