Commit 93581857 by Mark Shinwell Committed by Maxim Kuvyrkov

mips-modes.def: Add V8QI, V4HI and V2SI modes.

2008-06-15  Mark Shinwell  <shinwell@codesourcery.com>
	    Nathan Sidwell  <nathan@codesourcery.com>
	    Maxim Kuvyrkov  <maxim@codesourcery.com>
	    Richard Sandiford  <rdsandiford@googlemail.com>
	
	* config/mips/mips-modes.def: Add V8QI, V4HI and V2SI modes.
	* config/mips/mips-protos.h (mips_expand_vector_init): New.
	* config/mips/mips-ftypes.def: Add function types for Loongson-2E/2F
	builtins.
	* config/mips/mips.c (mips_split_doubleword_move): Handle new modes.
	(mips_hard_regno_mode_ok_p): Allow 64-bit vector modes for Loongson.
	(mips_vector_mode_supported_p): Add V2SImode, V4HImode and
	V8QImode cases.
	(LOONGSON_BUILTIN, LOONGSON_BUILTIN_ALIAS): New.
	(CODE_FOR_loongson_packsswh, CODE_FOR_loongson_packsshb,
	(CODE_FOR_loongson_packushb, CODE_FOR_loongson_paddw,
	(CODE_FOR_loongson_paddh, CODE_FOR_loongson_paddb,
	(CODE_FOR_loongson_paddsh, CODE_FOR_loongson_paddsb)
	(CODE_FOR_loongson_paddush, CODE_FOR_loongson_paddusb)
	(CODE_FOR_loongson_pmaxsh, CODE_FOR_loongson_pmaxub)
	(CODE_FOR_loongson_pminsh, CODE_FOR_loongson_pminub)
	(CODE_FOR_loongson_pmulhuh, CODE_FOR_loongson_pmulhh)
	(CODE_FOR_loongson_biadd, CODE_FOR_loongson_psubw)
	(CODE_FOR_loongson_psubh, CODE_FOR_loongson_psubb)
	(CODE_FOR_loongson_psubsh, CODE_FOR_loongson_psubsb)
	(CODE_FOR_loongson_psubush, CODE_FOR_loongson_psubusb)
	(CODE_FOR_loongson_punpckhbh, CODE_FOR_loongson_punpckhhw)
	(CODE_FOR_loongson_punpckhwd, CODE_FOR_loongson_punpcklbh)
	(CODE_FOR_loongson_punpcklhw, CODE_FOR_loongson_punpcklwd): New.
	(mips_builtins): Add Loongson builtins.
	(mips_loongson_2ef_bdesc): New.
	(mips_bdesc_arrays): Add mips_loongson_2ef_bdesc.
	(mips_builtin_vector_type): Handle unsigned versions of vector modes.
	(MIPS_ATYPE_UQI, MIPS_ATYPE_UDI, MIPS_ATYPE_V2SI, MIPS_ATYPE_UV2SI)
	(MIPS_ATYPE_V4HI, MIPS_ATYPE_UV4HI, MIPS_ATYPE_V8QI, MIPS_ATYPE_UV8QI):
	New.
	(mips_expand_vector_init): New.
	* config/mips/mips.h (HAVE_LOONGSON_VECTOR_MODES): New.
	(TARGET_CPU_CPP_BUILTINS): Define __mips_loongson_vector_rev
	if appropriate.
	* config/mips/mips.md: Add unspec numbers for Loongson
	builtins.  Include loongson.md.
	(MOVE64): Include Loongson vector modes.
	(SPLITF): Include Loongson vector modes.
	(HALFMODE): Handle Loongson vector modes.
	* config/mips/loongson.md: New.
	* config/mips/loongson.h: New.
	* config.gcc: Add loongson.h header for mips*-*-* targets.
	* doc/extend.texi (MIPS Loongson Built-in Functions): New.

2008-06-15  Mark Shinwell  <shinwell@codesourcery.com>

	* lib/target-supports.exp (check_effective_target_mips_loongson): New.
	* gcc.target/mips/loongson-simd.c: New.

Co-Authored-By: Maxim Kuvyrkov <maxim@codesourcery.com>
Co-Authored-By: Nathan Sidwell <nathan@codesourcery.com>
Co-Authored-By: Richard Sandiford <rdsandiford@googlemail.com>

From-SVN: r136800
parent 2454e4f6
2008-06-15 Mark Shinwell <shinwell@codesourcery.com>
Nathan Sidwell <nathan@codesourcery.com>
Maxim Kuvyrkov <maxim@codesourcery.com>
Richard Sandiford <rdsandiford@googlemail.com>
* config/mips/mips-modes.def: Add V8QI, V4HI and V2SI modes.
* config/mips/mips-protos.h (mips_expand_vector_init): New.
* config/mips/mips-ftypes.def: Add function types for Loongson-2E/2F
builtins.
* config/mips/mips.c (mips_split_doubleword_move): Handle new modes.
(mips_hard_regno_mode_ok_p): Allow 64-bit vector modes for Loongson.
(mips_vector_mode_supported_p): Add V2SImode, V4HImode and
V8QImode cases.
(LOONGSON_BUILTIN, LOONGSON_BUILTIN_ALIAS): New.
(CODE_FOR_loongson_packsswh, CODE_FOR_loongson_packsshb,
(CODE_FOR_loongson_packushb, CODE_FOR_loongson_paddw,
(CODE_FOR_loongson_paddh, CODE_FOR_loongson_paddb,
(CODE_FOR_loongson_paddsh, CODE_FOR_loongson_paddsb)
(CODE_FOR_loongson_paddush, CODE_FOR_loongson_paddusb)
(CODE_FOR_loongson_pmaxsh, CODE_FOR_loongson_pmaxub)
(CODE_FOR_loongson_pminsh, CODE_FOR_loongson_pminub)
(CODE_FOR_loongson_pmulhuh, CODE_FOR_loongson_pmulhh)
(CODE_FOR_loongson_biadd, CODE_FOR_loongson_psubw)
(CODE_FOR_loongson_psubh, CODE_FOR_loongson_psubb)
(CODE_FOR_loongson_psubsh, CODE_FOR_loongson_psubsb)
(CODE_FOR_loongson_psubush, CODE_FOR_loongson_psubusb)
(CODE_FOR_loongson_punpckhbh, CODE_FOR_loongson_punpckhhw)
(CODE_FOR_loongson_punpckhwd, CODE_FOR_loongson_punpcklbh)
(CODE_FOR_loongson_punpcklhw, CODE_FOR_loongson_punpcklwd): New.
(mips_builtins): Add Loongson builtins.
(mips_loongson_2ef_bdesc): New.
(mips_bdesc_arrays): Add mips_loongson_2ef_bdesc.
(mips_builtin_vector_type): Handle unsigned versions of vector modes.
(MIPS_ATYPE_UQI, MIPS_ATYPE_UDI, MIPS_ATYPE_V2SI, MIPS_ATYPE_UV2SI)
(MIPS_ATYPE_V4HI, MIPS_ATYPE_UV4HI, MIPS_ATYPE_V8QI, MIPS_ATYPE_UV8QI):
New.
(mips_expand_vector_init): New.
* config/mips/mips.h (HAVE_LOONGSON_VECTOR_MODES): New.
(TARGET_CPU_CPP_BUILTINS): Define __mips_loongson_vector_rev
if appropriate.
* config/mips/mips.md: Add unspec numbers for Loongson
builtins. Include loongson.md.
(MOVE64): Include Loongson vector modes.
(SPLITF): Include Loongson vector modes.
(HALFMODE): Handle Loongson vector modes.
* config/mips/loongson.md: New.
* config/mips/loongson.h: New.
* config.gcc: Add loongson.h header for mips*-*-* targets.
* doc/extend.texi (MIPS Loongson Built-in Functions): New.
2008-06-14 Joseph Myers <joseph@codesourcery.com> 2008-06-14 Joseph Myers <joseph@codesourcery.com>
* config.gcc (arc-*-elf*, avr-*-*, fr30-*-elf, frv-*-elf, * config.gcc (arc-*-elf*, avr-*-*, fr30-*-elf, frv-*-elf,
......
...@@ -307,6 +307,7 @@ m68k-*-*) ...@@ -307,6 +307,7 @@ m68k-*-*)
mips*-*-*) mips*-*-*)
cpu_type=mips cpu_type=mips
need_64bit_hwint=yes need_64bit_hwint=yes
extra_headers="loongson.h"
;; ;;
powerpc*-*-*) powerpc*-*-*)
cpu_type=rs6000 cpu_type=rs6000
......
...@@ -66,6 +66,24 @@ DEF_MIPS_FTYPE (1, (SF, SF)) ...@@ -66,6 +66,24 @@ DEF_MIPS_FTYPE (1, (SF, SF))
DEF_MIPS_FTYPE (2, (SF, SF, SF)) DEF_MIPS_FTYPE (2, (SF, SF, SF))
DEF_MIPS_FTYPE (1, (SF, V2SF)) DEF_MIPS_FTYPE (1, (SF, V2SF))
DEF_MIPS_FTYPE (2, (UDI, UDI, UDI))
DEF_MIPS_FTYPE (2, (UDI, UV2SI, UV2SI))
DEF_MIPS_FTYPE (2, (UV2SI, UV2SI, UQI))
DEF_MIPS_FTYPE (2, (UV2SI, UV2SI, UV2SI))
DEF_MIPS_FTYPE (2, (UV4HI, UV4HI, UQI))
DEF_MIPS_FTYPE (2, (UV4HI, UV4HI, USI))
DEF_MIPS_FTYPE (3, (UV4HI, UV4HI, UV4HI, UQI))
DEF_MIPS_FTYPE (3, (UV4HI, UV4HI, UV4HI, USI))
DEF_MIPS_FTYPE (2, (UV4HI, UV4HI, UV4HI))
DEF_MIPS_FTYPE (1, (UV4HI, UV8QI))
DEF_MIPS_FTYPE (2, (UV4HI, UV8QI, UV8QI))
DEF_MIPS_FTYPE (2, (UV8QI, UV4HI, UV4HI))
DEF_MIPS_FTYPE (1, (UV8QI, UV8QI))
DEF_MIPS_FTYPE (2, (UV8QI, UV8QI, UV8QI))
DEF_MIPS_FTYPE (1, (V2HI, SI)) DEF_MIPS_FTYPE (1, (V2HI, SI))
DEF_MIPS_FTYPE (2, (V2HI, SI, SI)) DEF_MIPS_FTYPE (2, (V2HI, SI, SI))
DEF_MIPS_FTYPE (3, (V2HI, SI, SI, SI)) DEF_MIPS_FTYPE (3, (V2HI, SI, SI, SI))
...@@ -81,12 +99,27 @@ DEF_MIPS_FTYPE (2, (V2SF, V2SF, V2SF)) ...@@ -81,12 +99,27 @@ DEF_MIPS_FTYPE (2, (V2SF, V2SF, V2SF))
DEF_MIPS_FTYPE (3, (V2SF, V2SF, V2SF, INT)) DEF_MIPS_FTYPE (3, (V2SF, V2SF, V2SF, INT))
DEF_MIPS_FTYPE (4, (V2SF, V2SF, V2SF, V2SF, V2SF)) DEF_MIPS_FTYPE (4, (V2SF, V2SF, V2SF, V2SF, V2SF))
DEF_MIPS_FTYPE (2, (V2SI, V2SI, UQI))
DEF_MIPS_FTYPE (2, (V2SI, V2SI, V2SI))
DEF_MIPS_FTYPE (2, (V2SI, V4HI, V4HI))
DEF_MIPS_FTYPE (2, (V4HI, V2SI, V2SI))
DEF_MIPS_FTYPE (2, (V4HI, V4HI, UQI))
DEF_MIPS_FTYPE (2, (V4HI, V4HI, USI))
DEF_MIPS_FTYPE (2, (V4HI, V4HI, V4HI))
DEF_MIPS_FTYPE (3, (V4HI, V4HI, V4HI, UQI))
DEF_MIPS_FTYPE (3, (V4HI, V4HI, V4HI, USI))
DEF_MIPS_FTYPE (1, (V4QI, SI)) DEF_MIPS_FTYPE (1, (V4QI, SI))
DEF_MIPS_FTYPE (2, (V4QI, V2HI, V2HI)) DEF_MIPS_FTYPE (2, (V4QI, V2HI, V2HI))
DEF_MIPS_FTYPE (1, (V4QI, V4QI)) DEF_MIPS_FTYPE (1, (V4QI, V4QI))
DEF_MIPS_FTYPE (2, (V4QI, V4QI, SI)) DEF_MIPS_FTYPE (2, (V4QI, V4QI, SI))
DEF_MIPS_FTYPE (2, (V4QI, V4QI, V4QI)) DEF_MIPS_FTYPE (2, (V4QI, V4QI, V4QI))
DEF_MIPS_FTYPE (2, (V8QI, V4HI, V4HI))
DEF_MIPS_FTYPE (1, (V8QI, V8QI))
DEF_MIPS_FTYPE (2, (V8QI, V8QI, V8QI))
DEF_MIPS_FTYPE (2, (VOID, SI, SI)) DEF_MIPS_FTYPE (2, (VOID, SI, SI))
DEF_MIPS_FTYPE (2, (VOID, V2HI, V2HI)) DEF_MIPS_FTYPE (2, (VOID, V2HI, V2HI))
DEF_MIPS_FTYPE (2, (VOID, V4QI, V4QI)) DEF_MIPS_FTYPE (2, (VOID, V4QI, V4QI))
...@@ -26,6 +26,7 @@ RESET_FLOAT_FORMAT (DF, mips_double_format); ...@@ -26,6 +26,7 @@ RESET_FLOAT_FORMAT (DF, mips_double_format);
FLOAT_MODE (TF, 16, mips_quad_format); FLOAT_MODE (TF, 16, mips_quad_format);
/* Vector modes. */ /* Vector modes. */
VECTOR_MODES (INT, 8); /* V8QI V4HI V2SI */
VECTOR_MODES (FLOAT, 8); /* V4HF V2SF */ VECTOR_MODES (FLOAT, 8); /* V4HF V2SF */
VECTOR_MODES (INT, 4); /* V4QI V2HI */ VECTOR_MODES (INT, 4); /* V4QI V2HI */
......
...@@ -303,4 +303,6 @@ union mips_gen_fn_ptrs ...@@ -303,4 +303,6 @@ union mips_gen_fn_ptrs
extern void mips_expand_atomic_qihi (union mips_gen_fn_ptrs, extern void mips_expand_atomic_qihi (union mips_gen_fn_ptrs,
rtx, rtx, rtx, rtx); rtx, rtx, rtx, rtx);
extern void mips_expand_vector_init (rtx, rtx);
#endif /* ! GCC_MIPS_PROTOS_H */ #endif /* ! GCC_MIPS_PROTOS_H */
...@@ -267,6 +267,12 @@ enum mips_code_readable_setting { ...@@ -267,6 +267,12 @@ enum mips_code_readable_setting {
|| mips_tune == PROCESSOR_74KF3_2) || mips_tune == PROCESSOR_74KF3_2)
#define TUNE_20KC (mips_tune == PROCESSOR_20KC) #define TUNE_20KC (mips_tune == PROCESSOR_20KC)
/* Whether vector modes and intrinsics for ST Microelectronics
Loongson-2E/2F processors should be enabled. In o32 pairs of
floating-point registers provide 64-bit values. */
#define TARGET_LOONGSON_VECTORS (TARGET_HARD_FLOAT_ABI \
&& TARGET_LOONGSON_2EF)
/* True if the pre-reload scheduler should try to create chains of /* True if the pre-reload scheduler should try to create chains of
multiply-add or multiply-subtract instructions. For example, multiply-add or multiply-subtract instructions. For example,
suppose we have: suppose we have:
...@@ -497,6 +503,10 @@ enum mips_code_readable_setting { ...@@ -497,6 +503,10 @@ enum mips_code_readable_setting {
builtin_define_std ("MIPSEL"); \ builtin_define_std ("MIPSEL"); \
builtin_define ("_MIPSEL"); \ builtin_define ("_MIPSEL"); \
} \ } \
\
/* Whether Loongson vector modes are enabled. */ \
if (TARGET_LOONGSON_VECTORS) \
builtin_define ("__mips_loongson_vector_rev"); \
\ \
/* Macros dependent on the C dialect. */ \ /* Macros dependent on the C dialect. */ \
if (preprocessing_asm_p ()) \ if (preprocessing_asm_p ()) \
......
...@@ -215,6 +215,30 @@ ...@@ -215,6 +215,30 @@
(UNSPEC_DPAQX_SA_W_PH 446) (UNSPEC_DPAQX_SA_W_PH 446)
(UNSPEC_DPSQX_S_W_PH 447) (UNSPEC_DPSQX_S_W_PH 447)
(UNSPEC_DPSQX_SA_W_PH 448) (UNSPEC_DPSQX_SA_W_PH 448)
;; ST Microelectronics Loongson-2E/2F.
(UNSPEC_LOONGSON_PAVG 500)
(UNSPEC_LOONGSON_PCMPEQ 501)
(UNSPEC_LOONGSON_PCMPGT 502)
(UNSPEC_LOONGSON_PEXTR 503)
(UNSPEC_LOONGSON_PINSR_0 504)
(UNSPEC_LOONGSON_PINSR_1 505)
(UNSPEC_LOONGSON_PINSR_2 506)
(UNSPEC_LOONGSON_PINSR_3 507)
(UNSPEC_LOONGSON_PMADD 508)
(UNSPEC_LOONGSON_PMOVMSK 509)
(UNSPEC_LOONGSON_PMULHU 510)
(UNSPEC_LOONGSON_PMULH 511)
(UNSPEC_LOONGSON_PMULL 512)
(UNSPEC_LOONGSON_PMULU 513)
(UNSPEC_LOONGSON_PASUBUB 514)
(UNSPEC_LOONGSON_BIADD 515)
(UNSPEC_LOONGSON_PSADBH 516)
(UNSPEC_LOONGSON_PSHUFH 517)
(UNSPEC_LOONGSON_PUNPCKH 518)
(UNSPEC_LOONGSON_PUNPCKL 519)
(UNSPEC_LOONGSON_PADDD 520)
(UNSPEC_LOONGSON_PSUBD 521)
] ]
) )
...@@ -500,7 +524,11 @@ ...@@ -500,7 +524,11 @@
;; 64-bit modes for which we provide move patterns. ;; 64-bit modes for which we provide move patterns.
(define_mode_iterator MOVE64 (define_mode_iterator MOVE64
[DI DF (V2SF "TARGET_HARD_FLOAT && TARGET_PAIRED_SINGLE_FLOAT")]) [DI DF
(V2SF "TARGET_HARD_FLOAT && TARGET_PAIRED_SINGLE_FLOAT")
(V2SI "TARGET_HARD_FLOAT && TARGET_LOONGSON_VECTORS")
(V4HI "TARGET_HARD_FLOAT && TARGET_LOONGSON_VECTORS")
(V8QI "TARGET_HARD_FLOAT && TARGET_LOONGSON_VECTORS")])
;; 128-bit modes for which we provide move patterns on 64-bit targets. ;; 128-bit modes for which we provide move patterns on 64-bit targets.
(define_mode_iterator MOVE128 [TI TF]) (define_mode_iterator MOVE128 [TI TF])
...@@ -527,6 +555,9 @@ ...@@ -527,6 +555,9 @@
[(DF "!TARGET_64BIT && TARGET_DOUBLE_FLOAT") [(DF "!TARGET_64BIT && TARGET_DOUBLE_FLOAT")
(DI "!TARGET_64BIT && TARGET_DOUBLE_FLOAT") (DI "!TARGET_64BIT && TARGET_DOUBLE_FLOAT")
(V2SF "!TARGET_64BIT && TARGET_PAIRED_SINGLE_FLOAT") (V2SF "!TARGET_64BIT && TARGET_PAIRED_SINGLE_FLOAT")
(V2SI "!TARGET_64BIT && TARGET_LOONGSON_VECTORS")
(V4HI "!TARGET_64BIT && TARGET_LOONGSON_VECTORS")
(V8QI "!TARGET_64BIT && TARGET_LOONGSON_VECTORS")
(TF "TARGET_64BIT && TARGET_FLOAT64")]) (TF "TARGET_64BIT && TARGET_FLOAT64")])
;; In GPR templates, a string like "<d>subu" will expand to "subu" in the ;; In GPR templates, a string like "<d>subu" will expand to "subu" in the
...@@ -579,7 +610,9 @@ ...@@ -579,7 +610,9 @@
;; This attribute gives the integer mode that has half the size of ;; This attribute gives the integer mode that has half the size of
;; the controlling mode. ;; the controlling mode.
(define_mode_attr HALFMODE [(DF "SI") (DI "SI") (V2SF "SI") (TF "DI")]) (define_mode_attr HALFMODE [(DF "SI") (DI "SI") (V2SF "SI")
(V2SI "SI") (V4HI "SI") (V8QI "SI")
(TF "DI")])
;; This attribute works around the early SB-1 rev2 core "F2" erratum: ;; This attribute works around the early SB-1 rev2 core "F2" erratum:
;; ;;
...@@ -6435,3 +6468,6 @@ ...@@ -6435,3 +6468,6 @@
; MIPS fixed-point instructions. ; MIPS fixed-point instructions.
(include "mips-fixed.md") (include "mips-fixed.md")
; ST-Microelectronics Loongson-2E/2F-specific patterns.
(include "loongson.md")
...@@ -6788,6 +6788,7 @@ instructions, but allow the compiler to schedule those calls. ...@@ -6788,6 +6788,7 @@ instructions, but allow the compiler to schedule those calls.
* X86 Built-in Functions:: * X86 Built-in Functions::
* MIPS DSP Built-in Functions:: * MIPS DSP Built-in Functions::
* MIPS Paired-Single Support:: * MIPS Paired-Single Support::
* MIPS Loongson Built-in Functions::
* PowerPC AltiVec Built-in Functions:: * PowerPC AltiVec Built-in Functions::
* SPARC VIS Built-in Functions:: * SPARC VIS Built-in Functions::
* SPU Built-in Functions:: * SPU Built-in Functions::
...@@ -8667,6 +8668,132 @@ value is the upper one. The opposite order applies to big-endian targets. ...@@ -8667,6 +8668,132 @@ value is the upper one. The opposite order applies to big-endian targets.
For example, the code above will set the lower half of @code{a} to For example, the code above will set the lower half of @code{a} to
@code{1.5} on little-endian targets and @code{9.1} on big-endian targets. @code{1.5} on little-endian targets and @code{9.1} on big-endian targets.
@node MIPS Loongson Built-in Functions
@subsection MIPS Loongson Built-in Functions
GCC provides intrinsics to access the SIMD instructions provided by the
ST Microelectronics Loongson-2E and -2F processors. These intrinsics,
available after inclusion of the @code{loongson.h} header file,
operate on the following 64-bit vector types:
@itemize
@item @code{uint8x8_t}, a vector of eight unsigned 8-bit integers;
@item @code{uint16x4_t}, a vector of four unsigned 16-bit integers;
@item @code{uint32x2_t}, a vector of two unsigned 32-bit integers;
@item @code{int8x8_t}, a vector of eight signed 8-bit integers;
@item @code{int16x4_t}, a vector of four signed 16-bit integers;
@item @code{int32x2_t}, a vector of two signed 32-bit integers.
@end itemize
The intrinsics provided are listed below; each is named after the
machine instruction to which it corresponds, with suffixes added as
appropriate to distinguish intrinsics that expand to the same machine
instruction yet have different argument types. Refer to the architecture
documentation for a description of the functionality of each
instruction.
@smallexample
int16x4_t packsswh (int32x2_t s, int32x2_t t);
int8x8_t packsshb (int16x4_t s, int16x4_t t);
uint8x8_t packushb (uint16x4_t s, uint16x4_t t);
uint32x2_t paddw_u (uint32x2_t s, uint32x2_t t);
uint16x4_t paddh_u (uint16x4_t s, uint16x4_t t);
uint8x8_t paddb_u (uint8x8_t s, uint8x8_t t);
int32x2_t paddw_s (int32x2_t s, int32x2_t t);
int16x4_t paddh_s (int16x4_t s, int16x4_t t);
int8x8_t paddb_s (int8x8_t s, int8x8_t t);
uint64_t paddd_u (uint64_t s, uint64_t t);
int64_t paddd_s (int64_t s, int64_t t);
int16x4_t paddsh (int16x4_t s, int16x4_t t);
int8x8_t paddsb (int8x8_t s, int8x8_t t);
uint16x4_t paddush (uint16x4_t s, uint16x4_t t);
uint8x8_t paddusb (uint8x8_t s, uint8x8_t t);
uint64_t pandn_ud (uint64_t s, uint64_t t);
uint32x2_t pandn_uw (uint32x2_t s, uint32x2_t t);
uint16x4_t pandn_uh (uint16x4_t s, uint16x4_t t);
uint8x8_t pandn_ub (uint8x8_t s, uint8x8_t t);
int64_t pandn_sd (int64_t s, int64_t t);
int32x2_t pandn_sw (int32x2_t s, int32x2_t t);
int16x4_t pandn_sh (int16x4_t s, int16x4_t t);
int8x8_t pandn_sb (int8x8_t s, int8x8_t t);
uint16x4_t pavgh (uint16x4_t s, uint16x4_t t);
uint8x8_t pavgb (uint8x8_t s, uint8x8_t t);
uint32x2_t pcmpeqw_u (uint32x2_t s, uint32x2_t t);
uint16x4_t pcmpeqh_u (uint16x4_t s, uint16x4_t t);
uint8x8_t pcmpeqb_u (uint8x8_t s, uint8x8_t t);
int32x2_t pcmpeqw_s (int32x2_t s, int32x2_t t);
int16x4_t pcmpeqh_s (int16x4_t s, int16x4_t t);
int8x8_t pcmpeqb_s (int8x8_t s, int8x8_t t);
uint32x2_t pcmpgtw_u (uint32x2_t s, uint32x2_t t);
uint16x4_t pcmpgth_u (uint16x4_t s, uint16x4_t t);
uint8x8_t pcmpgtb_u (uint8x8_t s, uint8x8_t t);
int32x2_t pcmpgtw_s (int32x2_t s, int32x2_t t);
int16x4_t pcmpgth_s (int16x4_t s, int16x4_t t);
int8x8_t pcmpgtb_s (int8x8_t s, int8x8_t t);
uint16x4_t pextrh_u (uint16x4_t s, int field);
int16x4_t pextrh_s (int16x4_t s, int field);
uint16x4_t pinsrh_0_u (uint16x4_t s, uint16x4_t t);
uint16x4_t pinsrh_1_u (uint16x4_t s, uint16x4_t t);
uint16x4_t pinsrh_2_u (uint16x4_t s, uint16x4_t t);
uint16x4_t pinsrh_3_u (uint16x4_t s, uint16x4_t t);
int16x4_t pinsrh_0_s (int16x4_t s, int16x4_t t);
int16x4_t pinsrh_1_s (int16x4_t s, int16x4_t t);
int16x4_t pinsrh_2_s (int16x4_t s, int16x4_t t);
int16x4_t pinsrh_3_s (int16x4_t s, int16x4_t t);
int32x2_t pmaddhw (int16x4_t s, int16x4_t t);
int16x4_t pmaxsh (int16x4_t s, int16x4_t t);
uint8x8_t pmaxub (uint8x8_t s, uint8x8_t t);
int16x4_t pminsh (int16x4_t s, int16x4_t t);
uint8x8_t pminub (uint8x8_t s, uint8x8_t t);
uint8x8_t pmovmskb_u (uint8x8_t s);
int8x8_t pmovmskb_s (int8x8_t s);
uint16x4_t pmulhuh (uint16x4_t s, uint16x4_t t);
int16x4_t pmulhh (int16x4_t s, int16x4_t t);
int16x4_t pmullh (int16x4_t s, int16x4_t t);
int64_t pmuluw (uint32x2_t s, uint32x2_t t);
uint8x8_t pasubub (uint8x8_t s, uint8x8_t t);
uint16x4_t biadd (uint8x8_t s);
uint16x4_t psadbh (uint8x8_t s, uint8x8_t t);
uint16x4_t pshufh_u (uint16x4_t dest, uint16x4_t s, uint8_t order);
int16x4_t pshufh_s (int16x4_t dest, int16x4_t s, uint8_t order);
uint16x4_t psllh_u (uint16x4_t s, uint8_t amount);
int16x4_t psllh_s (int16x4_t s, uint8_t amount);
uint32x2_t psllw_u (uint32x2_t s, uint8_t amount);
int32x2_t psllw_s (int32x2_t s, uint8_t amount);
uint16x4_t psrlh_u (uint16x4_t s, uint8_t amount);
int16x4_t psrlh_s (int16x4_t s, uint8_t amount);
uint32x2_t psrlw_u (uint32x2_t s, uint8_t amount);
int32x2_t psrlw_s (int32x2_t s, uint8_t amount);
uint16x4_t psrah_u (uint16x4_t s, uint8_t amount);
int16x4_t psrah_s (int16x4_t s, uint8_t amount);
uint32x2_t psraw_u (uint32x2_t s, uint8_t amount);
int32x2_t psraw_s (int32x2_t s, uint8_t amount);
uint32x2_t psubw_u (uint32x2_t s, uint32x2_t t);
uint16x4_t psubh_u (uint16x4_t s, uint16x4_t t);
uint8x8_t psubb_u (uint8x8_t s, uint8x8_t t);
int32x2_t psubw_s (int32x2_t s, int32x2_t t);
int16x4_t psubh_s (int16x4_t s, int16x4_t t);
int8x8_t psubb_s (int8x8_t s, int8x8_t t);
uint64_t psubd_u (uint64_t s, uint64_t t);
int64_t psubd_s (int64_t s, int64_t t);
int16x4_t psubsh (int16x4_t s, int16x4_t t);
int8x8_t psubsb (int8x8_t s, int8x8_t t);
uint16x4_t psubush (uint16x4_t s, uint16x4_t t);
uint8x8_t psubusb (uint8x8_t s, uint8x8_t t);
uint32x2_t punpckhwd_u (uint32x2_t s, uint32x2_t t);
uint16x4_t punpckhhw_u (uint16x4_t s, uint16x4_t t);
uint8x8_t punpckhbh_u (uint8x8_t s, uint8x8_t t);
int32x2_t punpckhwd_s (int32x2_t s, int32x2_t t);
int16x4_t punpckhhw_s (int16x4_t s, int16x4_t t);
int8x8_t punpckhbh_s (int8x8_t s, int8x8_t t);
uint32x2_t punpcklwd_u (uint32x2_t s, uint32x2_t t);
uint16x4_t punpcklhw_u (uint16x4_t s, uint16x4_t t);
uint8x8_t punpcklbh_u (uint8x8_t s, uint8x8_t t);
int32x2_t punpcklwd_s (int32x2_t s, int32x2_t t);
int16x4_t punpcklhw_s (int16x4_t s, int16x4_t t);
int8x8_t punpcklbh_s (int8x8_t s, int8x8_t t);
@end smallexample
@menu @menu
* Paired-Single Arithmetic:: * Paired-Single Arithmetic::
* Paired-Single Built-in Functions:: * Paired-Single Built-in Functions::
......
2008-06-15 Mark Shinwell <shinwell@codesourcery.com>
* lib/target-supports.exp (check_effective_target_mips_loongson): New.
* gcc.target/mips/loongson-simd.c: New.
2008-06-14 Simon Martin <simartin@users.sourceforge.net> 2008-06-14 Simon Martin <simartin@users.sourceforge.net>
PR c++/35320 PR c++/35320
......
...@@ -1249,6 +1249,17 @@ proc check_effective_target_arm_neon_hw { } { ...@@ -1249,6 +1249,17 @@ proc check_effective_target_arm_neon_hw { } {
} "-mfpu=neon -mfloat-abi=softfp"] } "-mfpu=neon -mfloat-abi=softfp"]
} }
# Return 1 if this a Loongson-2E or -2F target using an ABI that supports
# the Loongson vector modes.
proc check_effective_target_mips_loongson { } {
return [check_no_compiler_messages loongson assembly {
#if !defined(__mips_loongson_vector_rev)
#error FOO
#endif
}]
}
# Return 1 if this is a PowerPC target with floating-point registers. # Return 1 if this is a PowerPC target with floating-point registers.
proc check_effective_target_powerpc_fprs { } { proc check_effective_target_powerpc_fprs { } {
......
Markdown is supported
0% or
You are about to add 0 people to the discussion. Proceed with caution.
Finish editing this message first!
Please register or to comment