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lvzhengyang
riscv-gcc-1
Commits
92e014ca
Commit
92e014ca
authored
Aug 01, 2012
by
Richard Henderson
Committed by
Richard Henderson
Aug 01, 2012
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m32c: Don't use set_optab_handler
From-SVN: r190049
parent
d94b820b
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3 changed files
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27 additions
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22 deletions
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-22
gcc/ChangeLog
+7
-0
gcc/config/m32c/cond.md
+20
-3
gcc/config/m32c/m32c.c
+0
-19
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gcc/ChangeLog
View file @
92e014ca
2012-08-01 Richard Henderson <rth@redhat.com>
* config/m32c/m32c.c (TARGET_INIT_LIBFUNCS): Remove.
(m32c_init_libfuncs): Remove.
* config/m32c/cond.md (cstore<QHPSI>4_16): Rename from cstore<QHPSI>4.
(cstore<QHPSI>4): New expander.
2012-08-01 Richard Guenther <rguenther@suse.de>
2012-08-01 Richard Guenther <rguenther@suse.de>
* tree-flow-inline.h (referenced_var): Remove.
* tree-flow-inline.h (referenced_var): Remove.
...
...
gcc/config/m32c/cond.md
View file @
92e014ca
...
@@ -152,14 +152,31 @@
...
@@ -152,14 +152,31 @@
;; These are the pre-split patterns for the conditional sets.
;; These are the pre-split patterns for the conditional sets.
(define_insn_and_split "cstore
<mode>
4"
(define_expand "cstore
<mode>
4"
[
(set (match_operand:QI 0 "register_operand")
(match_operator:QI 1 "ordered_comparison_operator"
[
(match_operand:QHPSI 2 "mra_operand")
(match_operand:QHPSI 3 "mrai_operand")]))]
""
{
if (TARGET_A24)
{
rtx o = gen_reg_rtx (HImode);
emit_insn (gen_cstore
<mode>
4_24 (o, operands
[
1
]
,
operands
[
2
]
, operands
[
3
]
));
emit_move_insn (operands
[
0
]
, gen_lowpart (QImode, o));
DONE;
}
})
(define_insn_and_split "
*
cstore
<mode>
4_16"
[
(set (match_operand:QI 0 "register_operand" "=Rqi")
[
(set (match_operand:QI 0 "register_operand" "=Rqi")
(match_operator:QI 1 "ordered_comparison_operator"
(match_operator:QI 1 "ordered_comparison_operator"
[
(match_operand:QHPSI 2 "mra_operand" "RraSd")
[
(match_operand:QHPSI 2 "mra_operand" "RraSd")
(match_operand:QHPSI 3 "mrai_operand" "RraSdi")]))]
(match_operand:QHPSI 3 "mrai_operand" "RraSdi")]))]
"TARGET_A16"
"TARGET_A16"
"#"
"#"
"reload_completed"
"
&&
reload_completed"
[
(set (reg:CC FLG_REGNO)
[
(set (reg:CC FLG_REGNO)
(compare (match_dup 2)
(compare (match_dup 2)
(match_dup 3)))
(match_dup 3)))
...
@@ -176,7 +193,7 @@
...
@@ -176,7 +193,7 @@
(match_operand:QHPSI 3 "mrai_operand" "RraSdi")]))]
(match_operand:QHPSI 3 "mrai_operand" "RraSdi")]))]
"TARGET_A24"
"TARGET_A24"
"#"
"#"
"reload_completed"
"
&&
reload_completed"
[
(set (reg:CC FLG_REGNO)
[
(set (reg:CC FLG_REGNO)
(compare (match_dup 2)
(compare (match_dup 2)
(match_dup 3)))
(match_dup 3)))
...
...
gcc/config/m32c/m32c.c
View file @
92e014ca
...
@@ -1857,25 +1857,6 @@ m32c_trampoline_init (rtx m_tramp, tree fndecl, rtx chainval)
...
@@ -1857,25 +1857,6 @@ m32c_trampoline_init (rtx m_tramp, tree fndecl, rtx chainval)
#undef A0
#undef A0
}
}
/* Implicit Calls to Library Routines */
#undef TARGET_INIT_LIBFUNCS
#define TARGET_INIT_LIBFUNCS m32c_init_libfuncs
static
void
m32c_init_libfuncs
(
void
)
{
/* We do this because the M32C has an HImode operand, but the
M16C has an 8-bit operand. Since gcc looks at the match data
and not the expanded rtl, we have to reset the optab so that
the right modes are found. */
if
(
TARGET_A24
)
{
set_optab_handler
(
cstore_optab
,
QImode
,
CODE_FOR_cstoreqi4_24
);
set_optab_handler
(
cstore_optab
,
HImode
,
CODE_FOR_cstorehi4_24
);
set_optab_handler
(
cstore_optab
,
PSImode
,
CODE_FOR_cstorepsi4_24
);
}
}
/* Addressing Modes */
/* Addressing Modes */
/* The r8c/m32c family supports a wide range of non-orthogonal
/* The r8c/m32c family supports a wide range of non-orthogonal
...
...
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