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Commit 92835317 by Tejas Belagod Committed by Tejas Belagod
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aarch64-simd.md (vec_pack_trunc_<mode>, [...]): Swap for big-endian. 

2013-11-22  Tejas Belagod  <tejas.belagod@arm.com>

gcc/
	* config/aarch64/aarch64-simd.md (vec_pack_trunc_<mode>,
	vec_pack_trunc_v2df, vec_pack_trunc_df): Swap for big-endian.
	(reduc_<sur>plus_<mode>): Factorize V2DI into this.
	(reduc_<sur>plus_<mode>): Change this to reduc_splus_<mode> for floats
	and also change to float UNSPEC.
	(reduc_maxmin_uns>_<mode>): Remove V2DI.
	* config/aarch64/arm_neon.h (vaddv<q>_<suf><8,16,32,64>,
        vmaxv<q>_<suf><8,16,32,64>, vminv<q>_<suf><8,16,32,64>): Fix up scalar
	result access for big-endian.
        (__LANE0): New macro used to fix up lane access of 'across-lanes'
         intrinsics for big-endian.
	* config/aarch64/iterators.md (VDQV): Add V2DI.
	(VDQV_S): New.
	(vp): New mode attribute.

From-SVN: r205269
parent 8fcc1c1f
Showing with 36 additions and 29 deletions
gcc/ChangeLog
2013-11-22 Tejas Belagod <tejas.belagod@arm.com>
* config/aarch64/aarch64-simd.md (vec_pack_trunc_<mode>,
vec_pack_trunc_v2df, vec_pack_trunc_df): Swap for big-endian.
(reduc_<sur>plus_<mode>): Factorize V2DI into this.
(reduc_<sur>plus_<mode>): Change this to reduc_splus_<mode> for floats
and also change to float UNSPEC.
(reduc_maxmin_uns>_<mode>): Remove V2DI.
* config/aarch64/arm_neon.h (vaddv<q>_<suf><8,16,32,64>,
vmaxv<q>_<suf><8,16,32,64>, vminv<q>_<suf><8,16,32,64>): Fix up scalar
result access for big-endian.
(__LANE0): New macro used to fix up lane access of 'across-lanes'
intrinsics for big-endian.
* config/aarch64/iterators.md (VDQV): Add V2DI.
(VDQV_S): New.
(vp): New mode attribute.
2013-11-22 Tejas Belagod <tejas.belagod@arm.com>
* config/aarch64/aarch64-simd.md (vec_pack_trunc_<mode>,
vec_pack_trunc_v2df, vec_pack_trunc_df): Swap source ops for big-endian.
2013-11-22 Tejas Belagod <tejas.belagod@arm.com>
gcc/config/aarch64/aarch64-simd.md
......@@ -1557,19 +1557,10 @@
(unspec:VDQV [(match_operand:VDQV 1 "register_operand" "w")]
SUADDV))]
"TARGET_SIMD"
"addv\\t%<Vetype>0, %1.<Vtype>"
"add<VDQV:vp>\\t%<Vetype>0, %1.<Vtype>"
[(set_attr "type" "neon_reduc_add<q>")]
)
(define_insn "reduc_<sur>plus_v2di"
[(set (match_operand:V2DI 0 "register_operand" "=w")
(unspec:V2DI [(match_operand:V2DI 1 "register_operand" "w")]
SUADDV))]
"TARGET_SIMD"
"addp\\t%d0, %1.2d"
[(set_attr "type" "neon_reduc_add_q")]
)
(define_insn "reduc_<sur>plus_v2si"
[(set (match_operand:V2SI 0 "register_operand" "=w")
(unspec:V2SI [(match_operand:V2SI 1 "register_operand" "w")]
......@@ -1579,10 +1570,10 @@
[(set_attr "type" "neon_reduc_add")]
)
(define_insn "reduc_<sur>plus_<mode>"
(define_insn "reduc_splus_<mode>"
[(set (match_operand:V2F 0 "register_operand" "=w")
(unspec:V2F [(match_operand:V2F 1 "register_operand" "w")]
SUADDV))]
UNSPEC_FADDV))]
"TARGET_SIMD"
"faddp\\t%<Vetype>0, %1.<Vtype>"
[(set_attr "type" "neon_fp_reduc_add_<Vetype><q>")]
......@@ -1597,15 +1588,14 @@
[(set_attr "type" "neon_fp_reduc_add_s_q")]
)
(define_expand "reduc_<sur>plus_v4sf"
(define_expand "reduc_splus_v4sf"
[(set (match_operand:V4SF 0 "register_operand")
(unspec:V4SF [(match_operand:V4SF 1 "register_operand")]
SUADDV))]
UNSPEC_FADDV))]
"TARGET_SIMD"
{
rtx tmp = gen_reg_rtx (V4SFmode);
emit_insn (gen_aarch64_addpv4sf (tmp, operands[1]));
emit_insn (gen_aarch64_addpv4sf (operands[0], tmp));
emit_insn (gen_aarch64_addpv4sf (operands[0], operands[1]));
emit_insn (gen_aarch64_addpv4sf (operands[0], operands[0]));
DONE;
})
......@@ -1620,23 +1610,14 @@
;; 'across lanes' max and min ops.
(define_insn "reduc_<maxmin_uns>_<mode>"
[(set (match_operand:VDQV 0 "register_operand" "=w")
(unspec:VDQV [(match_operand:VDQV 1 "register_operand" "w")]
[(set (match_operand:VDQV_S 0 "register_operand" "=w")
(unspec:VDQV_S [(match_operand:VDQV_S 1 "register_operand" "w")]
MAXMINV))]
"TARGET_SIMD"
"<maxmin_uns_op>v\\t%<Vetype>0, %1.<Vtype>"
[(set_attr "type" "neon_reduc_minmax<q>")]
)
(define_insn "reduc_<maxmin_uns>_v2di"
[(set (match_operand:V2DI 0 "register_operand" "=w")
(unspec:V2DI [(match_operand:V2DI 1 "register_operand" "w")]
MAXMINV))]
"TARGET_SIMD"
"<maxmin_uns_op>p\\t%d0, %1.2d"
[(set_attr "type" "neon_reduc_minmax_q")]
)
(define_insn "reduc_<maxmin_uns>_v2si"
[(set (match_operand:V2SI 0 "register_operand" "=w")
(unspec:V2SI [(match_operand:V2SI 1 "register_operand" "w")]
......
gcc/config/aarch64/iterators.md
......@@ -108,7 +108,10 @@
(define_mode_iterator VALLDI [V8QI V16QI V4HI V8HI V2SI V4SI V2DI V2SF V4SF V2DF DI])
;; Vector modes for Integer reduction across lanes.
(define_mode_iterator VDQV [V8QI V16QI V4HI V8HI V4SI])
(define_mode_iterator VDQV [V8QI V16QI V4HI V8HI V4SI V2DI])
;; Vector modes(except V2DI) for Integer reduction across lanes.
(define_mode_iterator VDQV_S [V8QI V16QI V4HI V8HI V4SI])
;; All double integer narrow-able modes.
(define_mode_iterator VDN [V4HI V2SI DI])
......@@ -585,6 +588,12 @@
(V2DF "_q")
(QI "") (HI "") (SI "") (DI "") (SF "") (DF "")])
(define_mode_attr vp [(V8QI "v") (V16QI "v")
(V4HI "v") (V8HI "v")
(V2SI "p") (V4SI "v")
(V2DI "p") (V2DF "p")
(V2SF "p") (V4SF "v")])
;; -------------------------------------------------------------------
;; Code Iterators
;; -------------------------------------------------------------------
......
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