gcc/testsuite/ChangeLog:

2019-12-20  Stam Markianos-Wright  <stam.markianos-wright@arm.com>

	* lib/target-supports.exp 
	(check_effective_target_arm_v8_2a_i8mm_ok_nocache): New.
	(check_effective_target_arm_v8_2a_i8mm_ok): New.
	(add_options_for_arm_v8_2a_i8mm): New.
	(check_effective_target_arm_v8_2a_bf16_neon_ok_nocache): New.
	(check_effective_target_arm_v8_2a_bf16_neon_ok): New.
	(add_options_for_arm_v8_2a_bf16_neon): New.

gcc/Changelog:

2019-12-20  Stam Markianos-Wright  <stam.markianos-wright@arm.com>

	* doc/sourcebuild.texi
	(arm_v8_2a_bf16_neon_ok): Document new target supports option.
	(arm_v8_2a_i8mm_ok): Likewise.

From-SVN: r279648

gcc/ChangeLog

+2019-12-20  Stam Markianos-Wright  <stam.markianos-wright@arm.com>
+
+	* doc/sourcebuild.texi
+	(arm_v8_2a_bf16_neon_ok): Document new target supports option.
+	(arm_v8_2a_i8mm_ok): Likewise.
+
 2019-12-20  Jakub Jelinek  <jakub@redhat.com>
 
 	PR target/92841

gcc/doc/sourcebuild.texi

@@ -1877,6 +1877,16 @@ ARM target supports extensions to generate the @code{VFMAL} and @code{VFMLS}
 half-precision floating-point instructions available from ARMv8.2-A and
 onwards.  Some multilibs may be incompatible with these options.
 
+@item arm_v8_2a_bf16_neon_ok
+ARM target supports options to generate instructions from ARMv8.2-A with
+the BFloat16 extension (bf16). Some multilibs may be incompatible with these
+options.
+
+@item arm_v8_2a_i8mm_ok
+ARM target supports options to generate instructions from ARMv8.2-A with
+the 8-Bit Integer Matrix Multiply extension (i8mm). Some multilibs may be
+incompatible with these options.
+
 @item arm_prefer_ldrd_strd
 ARM target prefers @code{LDRD} and @code{STRD} instructions over
 @code{LDM} and @code{STM} instructions.

gcc/testsuite/ChangeLog

+2019-12-20  Stam Markianos-Wright  <stam.markianos-wright@arm.com>
+
+	* lib/target-supports.exp 
+	(check_effective_target_arm_v8_2a_i8mm_ok_nocache): New.
+	(check_effective_target_arm_v8_2a_i8mm_ok): New.
+	(add_options_for_arm_v8_2a_i8mm): New.
+	(check_effective_target_arm_v8_2a_bf16_neon_ok_nocache): New.
+	(check_effective_target_arm_v8_2a_bf16_neon_ok): New.
+	(add_options_for_arm_v8_2a_bf16_neon): New.
+
 2019-12-20  Roman Zhuykov  <zhroma@ispras.ru>
 
 	* gcc.dg/pr92951-1.c: Rename to ...

gcc/testsuite/lib/target-supports.exp

@@ -4781,6 +4781,49 @@ proc add_options_for_arm_v8_2a_dotprod_neon { flags } {
     return "$flags $et_arm_v8_2a_dotprod_neon_flags"
 }
 
+# Return 1 if the target supports ARMv8.2+i8mm Adv.SIMD Dot Product
+# instructions, 0 otherwise.  The test is valid for ARM and for AArch64.
+# Record the command line options needed.
+
+proc check_effective_target_arm_v8_2a_i8mm_ok_nocache { } {
+    global et_arm_v8_2a_i8mm_flags
+    set et_arm_v8_2a_i8mm_flags ""
+
+    if { ![istarget arm*-*-*] && ![istarget aarch64*-*-*] } {
+        return 0;
+    }
+
+    # Iterate through sets of options to find the compiler flags that
+    # need to be added to the -march option.
+    foreach flags {"" "-mfloat-abi=hard -mfpu=neon-fp-armv8" "-mfloat-abi=softfp -mfpu=neon-fp-armv8" } {
+        if { [check_no_compiler_messages_nocache \
+                  arm_v8_2a_i8mm_ok object {
+            #include <arm_neon.h>
+            #if !defined (__ARM_FEATURE_MATMUL_INT8)
+            #error "__ARM_FEATURE_MATMUL_INT8 not defined"
+            #endif
+        } "$flags -march=armv8.2-a+i8mm"] } {
+            set et_arm_v8_2a_i8mm_flags "$flags -march=armv8.2-a+i8mm"
+            return 1
+        }
+    }
+
+    return 0;
+}
+
+proc check_effective_target_arm_v8_2a_i8mm_ok { } {
+    return [check_cached_effective_target arm_v8_2a_i8mm_ok \
+                check_effective_target_arm_v8_2a_i8mm_ok_nocache]
+}
+
+proc add_options_for_arm_v8_2a_i8mm { flags } {
+    if { ! [check_effective_target_arm_v8_2a_i8mm_ok] } {
+        return "$flags"
+    }
+    global et_arm_v8_2a_i8mm_flags
+    return "$flags $et_arm_v8_2a_i8mm_flags"
+}
+
 # Return 1 if the target supports FP16 VFMAL and VFMSL
 # instructions, 0 otherwise.
 # Record the command line options needed.
@@ -4826,6 +4869,45 @@ proc add_options_for_arm_fp16fml_neon { flags } {
     return "$flags $et_arm_fp16fml_neon_flags"
 }
 
+# Return 1 if the target supports BFloat16 SIMD instructions, 0 otherwise.
+# The test is valid for ARM and for AArch64.
+
+proc check_effective_target_arm_v8_2a_bf16_neon_ok_nocache { } {
+    global et_arm_v8_2a_bf16_neon_flags
+    set et_arm_v8_2a_bf16_neon_flags ""
+
+    if { ![istarget arm*-*-*] && ![istarget aarch64*-*-*] } {
+        return 0;
+    }
+
+    foreach flags {"" "-mfloat-abi=hard -mfpu=neon-fp-armv8" "-mfloat-abi=softfp -mfpu=neon-fp-armv8" } {
+        if { [check_no_compiler_messages_nocache arm_v8_2a_bf16_neon_ok object {
+            #include <arm_neon.h>
+            #if !defined (__ARM_FEATURE_BF16_VECTOR_ARITHMETIC)
+            #error "__ARM_FEATURE_BF16_VECTOR_ARITHMETIC not defined"
+            #endif
+        } "$flags -march=armv8.2-a+bf16"] } {
+            set et_arm_v8_2a_bf16_neon_flags "$flags -march=armv8.2-a+bf16"
+            return 1
+        }
+    }
+
+    return 0;
+}
+
+proc check_effective_target_arm_v8_2a_bf16_neon_ok { } {
+    return [check_cached_effective_target arm_v8_2a_bf16_neon_ok \
+                check_effective_target_arm_v8_2a_bf16_neon_ok_nocache]
+}
+
+proc add_options_for_arm_v8_2a_bf16_neon { flags } {
+    if { ! [check_effective_target_arm_v8_2a_bf16_neon_ok] } {
+        return "$flags"
+    }
+    global et_arm_v8_2a_bf16_neon_flags
+    return "$flags $et_arm_v8_2a_bf16_neon_flags"
+}
+
 # Return 1 if the target supports executing ARMv8 NEON instructions, 0
 # otherwise.