Skip to content

R
riscv-gcc-1
Commit 9259f3b0 by David Edelsohn Committed by David Edelsohn
Options

{40x.md,603.md,6xx.md,7450.md,7xx.md,mpc.md, [...]: Change mult_compare to imul_compare. 

        * config/rs6000/{40x.md,603.md,6xx.md,7450.md,7xx.md,mpc.md,
        power4.md,rios1.md,rios2.md,rs64.md}: Change mult_compare to
        imul_compare.  Add lmul_compare.
        * config/rs6000/power4.md: Bump some latencies.  Model extra cycle
        in second pair of dispatch slots.  Model stores more accurately.
        Tweak multiply model.  Add bypasses for CR instructions dependent
        on complicated compares.
        * config/rs6000/rs6000.md (mulsi3): Name imul_compare patterns.
        (muldi3): Add lmul_compare patterns.
        * config/rs6000/rs6000.c (rs6000_variable_issue): Move FPLOAD_UX
        and FPSTORE_UX to split instructions and add COMPARE,
        DELAYED_COMPARE, IMUL_COMPARE, LMUL_COMPARE, IDIV, LDIV.
        (rs6000_adjust_cost): Add IMUL_COMPARE and LMUL_COMPARE.
        (rs6000_rtx_costs): Separate POWER4 multiply case.

From-SVN: r65135
parent 7fe317e4
Showing with 114 additions and 30 deletions
gcc/ChangeLog
2003-04-01 David Edelsohn <edelsohn@gnu.org>
* config/rs6000/{40x.md,603.md,6xx.md,7450.md,7xx.md,mpc.md,
power4.md,rios1.md,rios2.md,rs64.md}: Change mult_compare to
imul_compare. Add lmul_compare.
* config/rs6000/power4.md: Bump some latencies. Model extra cycle
in second pair of dispatch slots. Model stores more accurately.
Tweak multiply model. Add bypasses for CR instructions dependent
on complicated compares.
* config/rs6000/rs6000.md (mulsi3): Name imul_compare patterns.
(muldi3): Add lmul_compare patterns.
* config/rs6000/rs6000.c (rs6000_variable_issue): Move FPLOAD_UX
and FPSTORE_UX to split instructions and add COMPARE,
DELAYED_COMPARE, IMUL_COMPARE, LMUL_COMPARE, IDIV, LDIV.
(rs6000_adjust_cost): Add IMUL_COMPARE and LMUL_COMPARE.
(rs6000_rtx_costs): Separate POWER4 multiply case.
2003-04-01 Ulrich Weigand <uweigand@de.ibm.com>
* config/s390/s390.c (s390_fixup_clobbered_return_reg):
......
gcc/config/rs6000/40x.md
......@@ -46,12 +46,12 @@
"iu_40x,nothing,bpu_40x")
(define_insn_reservation "ppc403-imul" 4
(and (eq_attr "type" "imul,imul2,imul3,mult_compare")
(and (eq_attr "type" "imul,imul2,imul3,imul_compare")
(eq_attr "cpu" "ppc403"))
"iu_40x*4")
(define_insn_reservation "ppc405-imul" 5
(and (eq_attr "type" "imul,mult_compare")
(and (eq_attr "type" "imul,imul_compare")
(eq_attr "cpu" "ppc405"))
"iu_40x*4")
......
gcc/config/rs6000/603.md
......@@ -60,7 +60,7 @@
; This takes 2 or 3 cycles
(define_insn_reservation "ppc603-imul" 3
(and (eq_attr "type" "imul,mult_compare")
(and (eq_attr "type" "imul,imul_compare")
(eq_attr "cpu" "ppc603"))
"iu_603*2")
......
gcc/config/rs6000/6xx.md
......@@ -69,17 +69,17 @@
"iu1_6xx|iu2_6xx")
(define_insn_reservation "ppc604-imul" 4
(and (eq_attr "type" "imul,imul2,imul3,mult_compare")
(and (eq_attr "type" "imul,imul2,imul3,imul_compare")
(eq_attr "cpu" "ppc604"))
"mciu_6xx*2")
(define_insn_reservation "ppc604e-imul" 2
(and (eq_attr "type" "imul,imul2,imul3,mult_compare")
(and (eq_attr "type" "imul,imul2,imul3,imul_compare")
(eq_attr "cpu" "ppc604e"))
"mciu_6xx")
(define_insn_reservation "ppc620-imul" 5
(and (eq_attr "type" "imul,mult_compare")
(and (eq_attr "type" "imul,imul_compare")
(eq_attr "cpu" "ppc620,ppc630"))
"mciu_6xx*3")
......@@ -94,7 +94,7 @@
"mciu_6xx*3")
(define_insn_reservation "ppc620-lmul" 7
(and (eq_attr "type" "lmul")
(and (eq_attr "type" "lmul,lmul_compare")
(eq_attr "cpu" "ppc620,ppc630"))
"mciu_6xx*5")
......
gcc/config/rs6000/7450.md
......@@ -69,7 +69,7 @@
"ppc7450_du,(iu1_7450|iu2_7450|iu3_7450)")
(define_insn_reservation "ppc7450-imul" 4
(and (eq_attr "type" "imul,mult_compare")
(and (eq_attr "type" "imul,imul_compare")
(eq_attr "cpu" "ppc7450"))
"ppc7450_du,mciu_7450*2")
......
gcc/config/rs6000/7xx.md
......@@ -64,7 +64,7 @@
"ppc750_du,(iu1_7xx|iu2_7xx)")
(define_insn_reservation "ppc750-imul" 4
(and (eq_attr "type" "imul,mult_compare")
(and (eq_attr "type" "imul,imul_compare")
(eq_attr "cpu" "ppc750,ppc7400"))
"ppc750_du,iu1_7xx*4")
......
gcc/config/rs6000/8540.md
......@@ -90,7 +90,7 @@
;; Multiply
(define_insn_reservation "ppc8540_multiply" 4
(and (eq_attr "type" "imul,imul2,imul3,mult_compare")
(and (eq_attr "type" "imul,imul2,imul3,imul_compare")
(eq_attr "cpu" "ppc8540"))
"ppc8540_decode,ppc8540_issue+ppc8540_miu_stage0,ppc8540_miu_stage1,\
ppc8540_miu_stage2,ppc8540_miu_stage3,ppc8540_retire")
......
gcc/config/rs6000/mpc.md
......@@ -47,7 +47,7 @@
"iu_mpc")
(define_insn_reservation "mpccore-imul" 2
(and (eq_attr "type" "imul,imul2,imul3,mult_compare")
(and (eq_attr "type" "imul,imul2,imul3,imul_compare")
(eq_attr "cpu" "mpccore"))
"mciu_mpc")
......
gcc/config/rs6000/rios1.md
......@@ -56,7 +56,7 @@
"iu_rios1")
(define_insn_reservation "rios1-imul" 5
(and (eq_attr "type" "imul,mult_compare")
(and (eq_attr "type" "imul,imul_compare")
(eq_attr "cpu" "rios1"))
"iu_rios1*5")
......@@ -66,12 +66,12 @@
"iu_rios1*4")
(define_insn_reservation "rios1-imul3" 3
(and (eq_attr "type" "imul,mult_compare")
(and (eq_attr "type" "imul")
(eq_attr "cpu" "rios1"))
"iu_rios1*3")
(define_insn_reservation "ppc601-imul" 5
(and (eq_attr "type" "imul,imul2,imul3,mult_compare")
(and (eq_attr "type" "imul,imul2,imul3,imul_compare")
(eq_attr "cpu" "ppc601"))
"iu_rios1*5")
......
gcc/config/rs6000/rios2.md
......@@ -44,7 +44,7 @@
"iu1_rios2|iu2_rios2")
(define_insn_reservation "rios2-imul" 2
(and (eq_attr "type" "imul,imul2,imul3,mult_compare")
(and (eq_attr "type" "imul,imul2,imul3,imul_compare")
(eq_attr "cpu" "rios2"))
"iu1_rios2*2")
......
gcc/config/rs6000/rs6000.c
......@@ -12522,12 +12522,15 @@ rs6000_variable_issue (stream, verbose, insn, more)
{
enum attr_type type = get_attr_type (insn);
if (type == TYPE_LOAD_EXT_U || type == TYPE_LOAD_EXT_UX
|| type == TYPE_LOAD_UX || type == TYPE_STORE_UX
|| type == TYPE_FPLOAD_UX || type == TYPE_FPSTORE_UX)
|| type == TYPE_LOAD_UX || type == TYPE_STORE_UX)
return 0;
else if (type == TYPE_LOAD_U || type == TYPE_STORE_U
|| type == TYPE_FPLOAD_U || type == TYPE_FPSTORE_U
|| type == TYPE_LOAD_EXT || type == TYPE_DELAYED_CR)
|| type == TYPE_FPLOAD_UX || type == TYPE_FPSTORE_UX
|| type == TYPE_LOAD_EXT || type == TYPE_DELAYED_CR
|| type == TYPE_COMPARE || type == TYPE_DELAYED_COMPARE
|| type == TYPE_IMUL_COMPARE || type == TYPE_LMUL_COMPARE
|| type == TYPE_IDIV || type == TYPE_LDIV)
return more > 2 ? more - 2 : 0;
}
......@@ -12580,6 +12583,8 @@ rs6000_adjust_cost (insn, link, dep_insn, cost)
&& (get_attr_type (dep_insn) == TYPE_CMP
|| get_attr_type (dep_insn) == TYPE_COMPARE
|| get_attr_type (dep_insn) == TYPE_DELAYED_COMPARE
|| get_attr_type (dep_insn) == TYPE_IMUL_COMPARE
|| get_attr_type (dep_insn) == TYPE_LMUL_COMPARE
|| get_attr_type (dep_insn) == TYPE_FPCOMPARE
|| get_attr_type (dep_insn) == TYPE_CR_LOGICAL
|| get_attr_type (dep_insn) == TYPE_DELAYED_CR))
......@@ -13712,7 +13717,6 @@ rs6000_rtx_costs (x, code, outer_code, total)
case PROCESSOR_PPC620:
case PROCESSOR_PPC630:
case PROCESSOR_POWER4:
*total = (GET_CODE (XEXP (x, 1)) != CONST_INT
? GET_MODE (XEXP (x, 1)) != DImode
? COSTS_N_INSNS (5) : COSTS_N_INSNS (7)
......@@ -13721,6 +13725,13 @@ rs6000_rtx_costs (x, code, outer_code, total)
? COSTS_N_INSNS (3) : COSTS_N_INSNS (4));
return true;
case PROCESSOR_POWER4:
*total = (GET_CODE (XEXP (x, 1)) != CONST_INT
? GET_MODE (XEXP (x, 1)) != DImode
? COSTS_N_INSNS (5) : COSTS_N_INSNS (7)
: COSTS_N_INSNS (4));
return true;
default:
abort ();
}
......
gcc/config/rs6000/rs6000.md
......@@ -39,7 +39,7 @@
;; Define an insn type attribute. This is used in function unit delay
;; computations.
(define_attr "type" "integer,load,load_ext,load_ext_u,load_ext_ux,load_ux,load_u,store,store_ux,store_u,fpload,fpload_ux,fpload_u,fpstore,fpstore_ux,fpstore_u,vecload,vecstore,imul,imul2,imul3,lmul,idiv,ldiv,branch,cmp,fast_compare,compare,delayed_compare,mult_compare,fpcompare,cr_logical,delayed_cr,mfcr,mtcr,mtjmpr,fp,fpsimple,dmul,sdiv,ddiv,ssqrt,dsqrt,jmpreg,brinc,vecsimple,veccomplex,vecdiv,veccmp,veccmpsimple,vecperm,vecfloat,vecfdiv"
(define_attr "type" "integer,load,load_ext,load_ext_u,load_ext_ux,load_ux,load_u,store,store_ux,store_u,fpload,fpload_ux,fpload_u,fpstore,fpstore_ux,fpstore_u,vecload,vecstore,imul,imul2,imul3,lmul,idiv,ldiv,branch,cmp,fast_compare,compare,delayed_compare,imul_compare,lmul_compare,fpcompare,cr_logical,delayed_cr,mfcr,mtcr,mtjmpr,fp,fpsimple,dmul,sdiv,ddiv,ssqrt,dsqrt,jmpreg,brinc,vecsimple,veccomplex,vecdiv,veccmp,veccmpsimple,vecperm,vecfloat,vecfdiv"
(const_string "integer"))
;; Length (in bytes).
......@@ -1669,7 +1669,7 @@
(const_string "imul2")]
(const_string "imul")))])
(define_insn ""
(define_insn "*mulsi3_mq_internal1"
[(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
(compare:CC (mult:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r")
(match_operand:SI 2 "gpc_reg_operand" "r,r"))
......@@ -1680,7 +1680,7 @@
"@
{muls.|mullw.} %3,%1,%2
#"
[(set_attr "type" "mult_compare")
[(set_attr "type" "imul_compare")
(set_attr "length" "4,8")])
(define_split
......@@ -1699,7 +1699,7 @@
(const_int 0)))]
"")
(define_insn ""
(define_insn "*mulsi3_no_mq_internal1"
[(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
(compare:CC (mult:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r")
(match_operand:SI 2 "gpc_reg_operand" "r,r"))
......@@ -1709,7 +1709,7 @@
"@
{muls.|mullw.} %3,%1,%2
#"
[(set_attr "type" "mult_compare")
[(set_attr "type" "imul_compare")
(set_attr "length" "4,8")])
(define_split
......@@ -1726,7 +1726,7 @@
(const_int 0)))]
"")
(define_insn ""
(define_insn "*mulsi3_mq_internal2"
[(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
(compare:CC (mult:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r")
(match_operand:SI 2 "gpc_reg_operand" "r,r"))
......@@ -1738,7 +1738,7 @@
"@
{muls.|mullw.} %0,%1,%2
#"
[(set_attr "type" "mult_compare")
[(set_attr "type" "imul_compare")
(set_attr "length" "4,8")])
(define_split
......@@ -1758,7 +1758,7 @@
(const_int 0)))]
"")
(define_insn ""
(define_insn "*mulsi3_no_mq_internal2"
[(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
(compare:CC (mult:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r")
(match_operand:SI 2 "gpc_reg_operand" "r,r"))
......@@ -1769,7 +1769,7 @@
"@
{muls.|mullw.} %0,%1,%2
#"
[(set_attr "type" "mult_compare")
[(set_attr "type" "imul_compare")
(set_attr "length" "4,8")])
(define_split
......@@ -6023,6 +6023,62 @@
"mulld %0,%1,%2"
[(set_attr "type" "lmul")])
(define_insn "*muldi3_internal1"
[(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
(compare:CC (mult:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r")
(match_operand:DI 2 "gpc_reg_operand" "r,r"))
(const_int 0)))
(clobber (match_scratch:DI 3 "=r,r"))]
"TARGET_POWERPC64"
"@
mulld. %3,%1,%2
#"
[(set_attr "type" "lmul_compare")
(set_attr "length" "4,8")])
(define_split
[(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
(compare:CC (mult:DI (match_operand:DI 1 "gpc_reg_operand" "")
(match_operand:DI 2 "gpc_reg_operand" ""))
(const_int 0)))
(clobber (match_scratch:DI 3 ""))]
"TARGET_POWERPC64 && reload_completed"
[(set (match_dup 3)
(mult:DI (match_dup 1) (match_dup 2)))
(set (match_dup 0)
(compare:CC (match_dup 3)
(const_int 0)))]
"")
(define_insn "*muldi3_internal2"
[(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
(compare:CC (mult:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r")
(match_operand:DI 2 "gpc_reg_operand" "r,r"))
(const_int 0)))
(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
(mult:DI (match_dup 1) (match_dup 2)))]
"TARGET_POWERPC64"
"@
mulld. %0,%1,%2
#"
[(set_attr "type" "lmul_compare")
(set_attr "length" "4,8")])
(define_split
[(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
(compare:CC (mult:DI (match_operand:DI 1 "gpc_reg_operand" "")
(match_operand:DI 2 "gpc_reg_operand" ""))
(const_int 0)))
(set (match_operand:DI 0 "gpc_reg_operand" "")
(mult:DI (match_dup 1) (match_dup 2)))]
"TARGET_POWERPC64 && reload_completed"
[(set (match_dup 0)
(mult:DI (match_dup 1) (match_dup 2)))
(set (match_dup 3)
(compare:CC (match_dup 0)
(const_int 0)))]
"")
(define_insn "smuldi3_highpart"
[(set (match_operand:DI 0 "gpc_reg_operand" "=r")
(truncate:DI
......
gcc/config/rs6000/rs64.md
......@@ -47,7 +47,7 @@
"iu_rs64")
(define_insn_reservation "rs64a-imul" 20
(and (eq_attr "type" "imul,mult_compare")
(and (eq_attr "type" "imul,imul_compare")
(eq_attr "cpu" "rs64a"))
"mciu_rs64*13")
......@@ -62,7 +62,7 @@
"mciu_rs64*2")
(define_insn_reservation "rs64a-lmul" 34
(and (eq_attr "type" "lmul")
(and (eq_attr "type" "lmul,lmul_compare")
(eq_attr "cpu" "rs64a"))
"mciu_rs64*34")
......
Markdown is supported
0% or
You are about to add 0 people to the discussion. Proceed with caution.
Finish editing this message first!
Please register or to comment