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riscv-gcc-1
Commit 9254148e by Bill Schmidt Committed by William Schmidt
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rs6000.c (vspltis_constant): Fix most significant bit of zero. 

2014-02-19  Bill Schmidt  <wschmidt@linux.vnet.ibm.com>

	* config/rs6000/rs6000.c (vspltis_constant): Fix most significant
	bit of zero.

From-SVN: r207919
parent 55694175
Showing with 6 additions and 1 deletions
gcc/ChangeLog
2014-02-19 Bill Schmidt <wschmidt@linux.vnet.ibm.com>
* config/rs6000/rs6000.c (vspltis_constant): Fix most significant
bit of zero.
2014-02-19 H.J. Lu <hongjiu.lu@intel.com>
PR target/60207
......
gcc/config/rs6000/rs6000.c
......@@ -5020,7 +5020,7 @@ vspltis_constant (rtx op, unsigned step, unsigned copies)
val = const_vector_elt_as_int (op, BYTES_BIG_ENDIAN ? nunits - 1 : 0);
splat_val = val;
msb_val = val > 0 ? 0 : -1;
msb_val = val >= 0 ? 0 : -1;
/* Construct the value to be splatted, if possible. If not, return 0. */
for (i = 2; i <= copies; i *= 2)
......
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