sync-cache.c (__aarch64_sync_cache_range): Cast the results of (dcache_lsize -…

sync-cache.c (__aarch64_sync_cache_range): Cast the results of (dcache_lsize - 1) and (icache_lsize - 1) to the type...

2013-01-17  Yufeng Zhang  <yufeng.zhang@arm.com>

	* config/aarch64/sync-cache.c (__aarch64_sync_cache_range): Cast the
	results of (dcache_lsize - 1) and (icache_lsize - 1) to the type
	__UINTPTR_TYPE__; also cast 'base' to the same type before the
	alignment operation.

From-SVN: r195266

libgcc/ChangeLog

+2013-01-17  Yufeng Zhang  <yufeng.zhang@arm.com>
+
+	* config/aarch64/sync-cache.c (__aarch64_sync_cache_range): Cast the
+	results of (dcache_lsize - 1) and (icache_lsize - 1) to the type
+	__UINTPTR_TYPE__; also cast 'base' to the same type before the
+	alignment operation.
+
 2013-01-15  Sofiane Naci  <sofiane.naci@arm.com>
 
 	* config/aarch64/sync-cache.c (__aarch64_sync_cache_range): Update

libgcc/config/aarch64/sync-cache.c

@@ -40,7 +40,8 @@ __aarch64_sync_cache_range (const void *base, const void *end)
      as per the GNU definition of __clear_cache.  */
 
   /* Make the start address of the loop cache aligned.  */
-  address = (const char*) ((unsigned long) base & ~ (dcache_lsize - 1));
+  address = (const char*) ((__UINTPTR_TYPE__) base
+			   & ~ (__UINTPTR_TYPE__) (dcache_lsize - 1));
 
   for (address; address < (const char *) end; address += dcache_lsize)
     asm volatile ("dc\tcvau, %0"
@@ -51,7 +52,8 @@ __aarch64_sync_cache_range (const void *base, const void *end)
   asm volatile ("dsb\tish" : : : "memory");
 
   /* Make the start address of the loop cache aligned.  */
-  address = (const char*) ((unsigned long) base & ~ (icache_lsize - 1));
+  address = (const char*) ((__UINTPTR_TYPE__) base
+			   & ~ (__UINTPTR_TYPE__) (icache_lsize - 1));
 
   for (address; address < (const char *) end; address += icache_lsize)
     asm volatile ("ic\tivau, %0"