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riscv-gcc-1
Commit 9208e4b2 by David S. Miller Committed by David S. Miller
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sparc.c (const64_operand, [...]): Get it right when HOST_BITS_PER_WIDE_INT is not 64. 

	* config/sparc/sparc.c (const64_operand, const64_high_operand):
	Get it right when HOST_BITS_PER_WIDE_INT is not 64.
	(input_operand): Fixup test for what we accept for constant
	integers.
	(sparc_emit_set_const32, sparc_emit_set_symbolic_const64): Give
	set VOIDmode.
	(safe_constDI): Remove.
	(sparc_emit_set_safe_HIGH64, gen_safe_SET64, gen_safe_OR64,
	gen_safe_XOR64): New functions.
	(sparc_emit_set_const64_quick1, sparc_emit_set_const64_quick2,
	sparc_emit_set_const64_longway, sparc_emit_set_const64): Use
	them.
	* config/sparc/sparc.md (define_insn xordi3_sp64_dbl): Only make
	available when HOST_BITS_PER_WIDE_INT is not 64.
	(define_insn movdi_sp64_dbl, movdi_const64_special): Likewise and
	move before movdi_insn_sp64 pattern.
	(define_insn movdi_lo_sum_sp64_dbl, movdi_high_sp64_dbl): Remove.
	(define_insn sethi_di_medlow, seth44, setm44, sethh): Use
	symbolic_operand as predicate for second operand.
	(DImode minus split on arch32, negsi2 expander, one_cmplsi2
	expander): Give set VOIDmode.

From-SVN: r21724
parent a2cd38a9
Showing with 55 additions and 29 deletions
gcc/ChangeLog
Fri Aug 14 00:34:34 1998 David S. Miller <davem@pierdol.cobaltmicro.com>
* config/sparc/sparc.c (const64_operand, const64_high_operand):
Get it right when HOST_BITS_PER_WIDE_INT is not 64.
(input_operand): Fixup test for what we accept for constant
integers.
(sparc_emit_set_const32, sparc_emit_set_symbolic_const64): Give
set VOIDmode.
(safe_constDI): Remove.
(sparc_emit_set_safe_HIGH64, gen_safe_SET64, gen_safe_OR64,
gen_safe_XOR64): New functions.
(sparc_emit_set_const64_quick1, sparc_emit_set_const64_quick2,
sparc_emit_set_const64_longway, sparc_emit_set_const64): Use
them.
* config/sparc/sparc.md (define_insn xordi3_sp64_dbl): Only make
available when HOST_BITS_PER_WIDE_INT is not 64.
(define_insn movdi_sp64_dbl, movdi_const64_special): Likewise and
move before movdi_insn_sp64 pattern.
(define_insn movdi_lo_sum_sp64_dbl, movdi_high_sp64_dbl): Remove.
(define_insn sethi_di_medlow, seth44, setm44, sethh): Use
symbolic_operand as predicate for second operand.
(DImode minus split on arch32, negsi2 expander, one_cmplsi2
expander): Give set VOIDmode.
Fri Aug 14 01:45:06 1998 Mumit Khan <khan@xraylith.wisc.edu>
* i386/cygwin32 (DEFAULT_PCC_STRUCT_RETURN): Define.
......
gcc/config/sparc/sparc.md
......@@ -2328,6 +2328,24 @@
[(set_attr "type" "store,load,*,*,*,*,fpstore,fpload,*,*,*")
(set_attr "length" "1,1,2,2,2,2,1,1,2,2,2")])
(define_insn "*movdi_sp64_dbl"
[(set (match_operand:DI 0 "register_operand" "=r")
(match_operand:DI 1 "const64_operand" ""))]
"(TARGET_ARCH64
&& HOST_BITS_PER_WIDE_INT != 64)"
"mov\\t%1, %0"
[(set_attr "type" "move")
(set_attr "length" "1")])
(define_insn "*movdi_const64_special"
[(set (match_operand:DI 0 "register_operand" "=r")
(match_operand:DI 1 "const64_high_operand" ""))]
"(TARGET_ARCH64
&& HOST_BITS_PER_WIDE_INT != 64)"
"sethi\\t%%hi(%a1), %0"
[(set_attr "type" "move")
(set_attr "length" "1")])
(define_insn "*movdi_insn_sp64"
[(set (match_operand:DI 0 "general_operand" "=r,r,r,r,m,?e,?e,?m")
(match_operand:DI 1 "input_operand" "rI,K,J,m,rJ,e,m,e"))]
......@@ -2346,7 +2364,7 @@
[(set_attr "type" "move,move,move,load,store,fpmove,fpload,fpstore")
(set_attr "length" "1")])
;; The following two are generated by sparc_emit_set_const64
;; The following are generated by sparc_emit_set_const64
(define_insn "*movdi_lo_sum_sp64_cint"
[(set (match_operand:DI 0 "register_operand" "=r")
(lo_sum:DI (match_operand:DI 1 "register_operand" "r")
......@@ -2356,15 +2374,6 @@
[(set_attr "type" "ialu")
(set_attr "length" "1")])
(define_insn "*movdi_lo_sum_sp64_dbl"
[(set (match_operand:DI 0 "register_operand" "=r")
(lo_sum:DI (match_operand:DI 1 "register_operand" "r")
(match_operand:DI 2 "const64_operand" "")))]
"TARGET_ARCH64"
"or\\t%1, %%lo(%a2), %0"
[(set_attr "type" "ialu")
(set_attr "length" "1")])
(define_insn "*movdi_high_sp64_cint"
[(set (match_operand:DI 0 "register_operand" "=r")
(high:DI (match_operand:DI 1 "const_int_operand" "in")))]
......@@ -2373,14 +2382,6 @@
[(set_attr "type" "move")
(set_attr "length" "1")])
(define_insn "*movdi_high_sp64_dbl"
[(set (match_operand:DI 0 "register_operand" "=r")
(high:DI (match_operand:DI 1 "const64_high_operand" "")))]
"TARGET_ARCH64"
"sethi\\t%%hi(%a1), %0"
[(set_attr "type" "move")
(set_attr "length" "1")])
;; ??? revisit this...
(define_insn "move_label_di"
[(set (match_operand:DI 0 "register_operand" "=r")
......@@ -2425,7 +2426,7 @@
(define_insn "*sethi_di_medlow"
[(set (match_operand:DI 0 "register_operand" "=r")
(high:DI (match_operand:DI 1 "" "")))]
(high:DI (match_operand:DI 1 "symbolic_operand" "")))]
"TARGET_CM_MEDLOW && check_pic (1)"
"sethi\\t%%hi(%a1), %0"
[(set_attr "type" "move")
......@@ -2441,7 +2442,7 @@
(define_insn "seth44"
[(set (match_operand:DI 0 "register_operand" "=r")
(high:DI (unspec:DI [(match_operand:DI 1 "" "")] 6)))]
(high:DI (unspec:DI [(match_operand:DI 1 "symbolic_operand" "")] 6)))]
"TARGET_CM_MEDMID"
"sethi\\t%%h44(%a1), %0"
[(set_attr "type" "move")
......@@ -2450,7 +2451,7 @@
(define_insn "setm44"
[(set (match_operand:DI 0 "register_operand" "=r")
(lo_sum:DI (match_operand:DI 1 "register_operand" "r")
(unspec:DI [(match_operand:DI 2 "" "")] 7)))]
(unspec:DI [(match_operand:DI 2 "symbolic_operand" "")] 7)))]
"TARGET_CM_MEDMID"
"or\\t%1, %%m44(%a2), %0"
[(set_attr "type" "move")
......@@ -2466,7 +2467,7 @@
(define_insn "sethh"
[(set (match_operand:DI 0 "register_operand" "=r")
(high:DI (unspec:DI [(match_operand:DI 1 "" "")] 9)))]
(high:DI (unspec:DI [(match_operand:DI 1 "symbolic_operand" "")] 9)))]
"TARGET_CM_MEDANY"
"sethi\\t%%hh(%a1), %0"
[(set_attr "type" "move")
......@@ -2474,7 +2475,7 @@
(define_insn "setlm"
[(set (match_operand:DI 0 "register_operand" "=r")
(high:DI (unspec:DI [(match_operand:DI 1 "" "")] 10)))]
(high:DI (unspec:DI [(match_operand:DI 1 "symbolic_operand" "")] 10)))]
"TARGET_CM_MEDANY"
"sethi\\t%%lm(%a1), %0"
[(set_attr "type" "move")
......@@ -4673,7 +4674,7 @@
if ((lowp == const0_rtx)
&& (operands[0] == operands[1]))
{
emit_insn (gen_rtx_SET (SImode,
emit_insn (gen_rtx_SET (VOIDmode,
gen_highpart (SImode, operands[0]),
gen_rtx_MINUS (SImode,
gen_highpart (SImode, operands[1]),
......@@ -5652,7 +5653,8 @@
[(set (match_operand:DI 0 "register_operand" "=r")
(xor:DI (match_operand:DI 1 "register_operand" "%r")
(match_operand:DI 2 "const64_operand" "")))]
"TARGET_ARCH64"
"(TARGET_ARCH64
&& HOST_BITS_PER_WIDE_INT != 64)"
"xor\\t%1, %2, %0"
[(set_attr "type" "ialu")
(set_attr "length" "1")])
......@@ -5971,8 +5973,8 @@
{
rtx zero_reg = gen_reg_rtx (SImode);
emit_insn (gen_rtx_SET (SImode, zero_reg, const0_rtx));
emit_insn (gen_rtx_SET (SImode, operands[0],
emit_insn (gen_rtx_SET (VOIDmode, zero_reg, const0_rtx));
emit_insn (gen_rtx_SET (VOIDmode, operands[0],
gen_rtx_MINUS (SImode, zero_reg,
operands[1])));
DONE;
......@@ -6078,8 +6080,8 @@
{
rtx zero_reg = gen_reg_rtx (SImode);
emit_insn (gen_rtx_SET (SImode, zero_reg, const0_rtx));
emit_insn (gen_rtx_SET (SImode,
emit_insn (gen_rtx_SET (VOIDmode, zero_reg, const0_rtx));
emit_insn (gen_rtx_SET (VOIDmode,
operands[0],
gen_rtx_NOT (SImode,
gen_rtx_XOR (SImode,
......
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