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riscv-gcc-1
Commit 91f0226f by Michael Meissner
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Fix indexing off arg ptr & push of byte values. 

From-SVN: r7994
parent e9954ee4
Showing with 16 additions and 13 deletions
gcc/config/i386/i386.c
...@@ -1076,6 +1076,15 @@ legitimate_address_p (mode, addr, strict) ...@@ -1076,6 +1076,15 @@ legitimate_address_p (mode, addr, strict)
else else
disp = addr; /* displacement */ disp = addr; /* displacement */
/* Allow arg pointer and stack pointer as index if there is not scaling */
if (base && indx && !scale
&& (indx == arg_pointer_rtx || indx == stack_pointer_rtx))
{
rtx tmp = base;
base = indx;
indx = tmp;
}
/* Validate base register */ /* Validate base register */
if (base) if (base)
{ {
......
gcc/config/i386/i386.h
...@@ -498,7 +498,7 @@ enum reg_class ...@@ -498,7 +498,7 @@ enum reg_class
0x3, /* AD_REGS */ \ 0x3, /* AD_REGS */ \
0xf, /* Q_REGS */ \ 0xf, /* Q_REGS */ \
0x10, 0x20, /* SIREG, DIREG */ \ 0x10, 0x20, /* SIREG, DIREG */ \
0x1007f, /* INDEX_REGS */ \ 0x07f, /* INDEX_REGS */ \
0x100ff, /* GENERAL_REGS */ \ 0x100ff, /* GENERAL_REGS */ \
0x0100, 0x0200, /* FP_TOP_REG, FP_SECOND_REG */ \ 0x0100, 0x0200, /* FP_TOP_REG, FP_SECOND_REG */ \
0xff00, /* FLOAT_REGS */ \ 0xff00, /* FLOAT_REGS */ \
......
gcc/config/i386/i386.md
...@@ -778,8 +778,7 @@ ...@@ -778,8 +778,7 @@
else if (TARGET_MOVE else if (TARGET_MOVE
&& (reload_in_progress | reload_completed) == 0 && (reload_in_progress | reload_completed) == 0
&& GET_CODE (operands[0]) == MEM && GET_CODE (operands[0]) == MEM
&& GET_CODE (operands[1]) == MEM && GET_CODE (operands[1]) == MEM)
&& (!TARGET_386 || !push_operand (operands[0], SImode)))
{ {
operands[1] = force_reg (SImode, operands[1]); operands[1] = force_reg (SImode, operands[1]);
} }
...@@ -842,8 +841,7 @@ ...@@ -842,8 +841,7 @@
if (TARGET_MOVE if (TARGET_MOVE
&& (reload_in_progress | reload_completed) == 0 && (reload_in_progress | reload_completed) == 0
&& GET_CODE (operands[0]) == MEM && GET_CODE (operands[0]) == MEM
&& GET_CODE (operands[1]) == MEM && GET_CODE (operands[1]) == MEM)
&& (!TARGET_386 || !push_operand (operands[0], HImode)))
{ {
operands[1] = force_reg (HImode, operands[1]); operands[1] = force_reg (HImode, operands[1]);
} }
...@@ -892,8 +890,7 @@ ...@@ -892,8 +890,7 @@
if (TARGET_MOVE if (TARGET_MOVE
&& (reload_in_progress | reload_completed) == 0 && (reload_in_progress | reload_completed) == 0
&& GET_CODE (operands[0]) == MEM && GET_CODE (operands[0]) == MEM
&& GET_CODE (operands[1]) == MEM && GET_CODE (operands[1]) == MEM)
&& (!TARGET_386 || !push_operand (operands[0], HImode)))
{ {
operands[1] = force_reg (HImode, operands[1]); operands[1] = force_reg (HImode, operands[1]);
} }
...@@ -969,8 +966,7 @@ ...@@ -969,8 +966,7 @@
if (TARGET_MOVE if (TARGET_MOVE
&& (reload_in_progress | reload_completed) == 0 && (reload_in_progress | reload_completed) == 0
&& GET_CODE (operands[0]) == MEM && GET_CODE (operands[0]) == MEM
&& GET_CODE (operands[1]) == MEM && GET_CODE (operands[1]) == MEM)
&& (!TARGET_386 || !push_operand (operands[0], QImode)))
{ {
operands[1] = force_reg (QImode, operands[1]); operands[1] = force_reg (QImode, operands[1]);
} }
...@@ -1024,8 +1020,7 @@ ...@@ -1024,8 +1020,7 @@
if (TARGET_MOVE if (TARGET_MOVE
&& (reload_in_progress | reload_completed) == 0 && (reload_in_progress | reload_completed) == 0
&& GET_CODE (operands[0]) == MEM && GET_CODE (operands[0]) == MEM
&& GET_CODE (operands[1]) == MEM && GET_CODE (operands[1]) == MEM)
&& (!TARGET_386 || !push_operand (operands[0], QImode)))
{ {
operands[1] = force_reg (QImode, operands[1]); operands[1] = force_reg (QImode, operands[1]);
} }
...@@ -1384,8 +1379,7 @@ ...@@ -1384,8 +1379,7 @@
if (TARGET_MOVE if (TARGET_MOVE
&& (reload_in_progress | reload_completed) == 0 && (reload_in_progress | reload_completed) == 0
&& GET_CODE (operands[0]) == MEM && GET_CODE (operands[0]) == MEM
&& GET_CODE (operands[1]) == MEM && GET_CODE (operands[1]) == MEM)
&& (!TARGET_386 || !push_operand (operands[0], QImode)))
{ {
operands[1] = force_reg (DImode, operands[1]); operands[1] = force_reg (DImode, operands[1]);
} }
......
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