[ARC] Refurbish and improve prologue/epilogue functions.

Reimplement how prologue and epilogue is emitted to accomodate
enter/leave instructions, as well as improving the size of the
existing techinques.

The following modifications are added:

- millicode thunk calls can be now selected regardless of the
  optimization level. However they are enabled for size optimizations
  by default.  Also, the millicode optimization is turned off when we
  compile for long jumps.

- the compiler is able to use enter/leave instructions for prologue
  and epilogue. As these instructions are not ABI compatible we gurad
  them under a switch (i.e., -mcode-density-frame). When this option
  is on, the compiler will try emitting enter/leave instructions, if
  not, then millicode thunk calls (if enabled), and latter the regular
  push/pop instructions.

- The prologue/epilogue is now optimized to use pointer walks, hence
  improving the chance to have push_s/pop_s instructions emitted. It
  also tries to combine the stack adjustments with load/store
  operations.

gcc/
xxxxx-xx-xx  Claudiu Zissulescu  <claziss@synopsys.com>

        * common/config/arc/arc-common.c (arc_option_optimization_table):
        Millicode optimization is default on for size optimizations.
        * config/arc/arc-protos.h (arc_check_multi): New function.
        * config/arc/arc.c (RTX_OK_FOR_OFFSET_P): Rearange.
        (ENTER_LEAVE_START_REG): Define.
        (ENTER_LEAVE_END_REG): Likewise.
        (arc_override_options): Disable millicode when long calls option
        is on.
        (arc_frame_info): Change it from int to bool.
        (arc_compute_frame_size): Clean up.
        (arc_save_restore): Remove.
        (frame_save_reg): New function.
        (frame_restore_reg): Likewise.
        (arc_enter_leave_p): Likewise.
        (arc_save_callee_saves): Likewise.
        (arc_restore_callee_saves): Likewise.
        (arc_save_callee_enter): Likewise.
        (arc_restore_callee_leave): Likewise.
        (arc_save_callee_milli): Likewise.
        (arc_restore_callee_milli): Likewise.
        (arc_expand_prologue): Reimplement to emit enter/leave
        instructions.
        (arc_expand_epilogue): Likewise.
        (arc_check_multi): New function.
        * config/arc/arc.md (push_multi_fp): New pattern.
        (push_multi_fp_blink): Likewise.
        (pop_multi_fp): Likewise.
        (pop_multi_fp_blink): Likewise.
        (pop_multi_fp_ret): Likewise.
        (pop_multi_fp_blink_ret): Likewise.
        * config/arc/arc.opt (mmillicode): Update option.
        (mcode-density-frame): New option.
        * config/arc/predicates.md (push_multi_operand): New predicate.
        (pop_multi_operand): Likewise.
        * doc/invoke.texi (ARC): Update ARC options information.

gcc/testsuite
xxxxx-xx-xx  Claudiu Zissulescu  <claziss@synopsys.com>

        * gcc.target/arc/firq-1.c: Update test.
        * gcc.target/arc/firq-3.c: Likewise.
        * gcc.target/arc/firq-4.c: Likewise.
        * gcc.target/arc/interrupt-6.c: Likewise.

From-SVN: r266065

gcc/ChangeLog

 2018-11-13  Claudiu Zissulescu  <claziss@synopsys.com>
 
+	* common/config/arc/arc-common.c (arc_option_optimization_table):
+	Millicode optimization is default on for size optimizations.
+	* config/arc/arc-protos.h (arc_check_multi): New function.
+	* config/arc/arc.c (RTX_OK_FOR_OFFSET_P): Rearange.
+	(ENTER_LEAVE_START_REG): Define.
+	(ENTER_LEAVE_END_REG): Likewise.
+	(arc_override_options): Disable millicode when long calls option
+	is on.
+	(arc_frame_info): Change it from int to bool.
+	(arc_compute_frame_size): Clean up.
+	(arc_save_restore): Remove.
+	(frame_save_reg): New function.
+	(frame_restore_reg): Likewise.
+	(arc_enter_leave_p): Likewise.
+	(arc_save_callee_saves): Likewise.
+	(arc_restore_callee_saves): Likewise.
+	(arc_save_callee_enter): Likewise.
+	(arc_restore_callee_leave): Likewise.
+	(arc_save_callee_milli): Likewise.
+	(arc_restore_callee_milli): Likewise.
+	(arc_expand_prologue): Reimplement to emit enter/leave
+	instructions.
+	(arc_expand_epilogue): Likewise.
+	(arc_check_multi): New function.
+	* config/arc/arc.md (push_multi_fp): New pattern.
+	(push_multi_fp_blink): Likewise.
+	(pop_multi_fp): Likewise.
+	(pop_multi_fp_blink): Likewise.
+	(pop_multi_fp_ret): Likewise.
+	(pop_multi_fp_blink_ret): Likewise.
+	* config/arc/arc.opt (mmillicode): Update option.
+	(mcode-density-frame): New option.
+	* config/arc/predicates.md (push_multi_operand): New predicate.
+	(pop_multi_operand): Likewise.
+	* doc/invoke.texi (ARC): Update ARC options information.
+
+
+2018-11-13  Claudiu Zissulescu  <claziss@synopsys.com>
+
 	* config/arc/arc-protos.h (gen_operands_ldd_std): Add.
 	* config/arc/arc.c (operands_ok_ldd_std): New function.
 	(mem_ok_for_ldd_std): Likewise.

gcc/common/config/arc/arc-common.c

@@ -59,6 +59,7 @@ static const struct default_options arc_option_optimization_table[] =
     { OPT_LEVELS_SIZE, OPT_mq_class, NULL, 1 },
     { OPT_LEVELS_SIZE, OPT_mcase_vector_pcrel, NULL, 1 },
     { OPT_LEVELS_SIZE, OPT_msize_level_, NULL, 3 },
+    { OPT_LEVELS_SIZE, OPT_mmillicode, NULL, 1 },
     { OPT_LEVELS_1_PLUS, OPT_fomit_frame_pointer, NULL, 1 },
     { OPT_LEVELS_3_PLUS_SPEED_ONLY, OPT_msize_level_, NULL, 0 },
     { OPT_LEVELS_3_PLUS_SPEED_ONLY, OPT_malign_call, NULL, 1 },

gcc/config/arc/arc-protos.h

@@ -45,8 +45,8 @@ extern bool compact_memory_operand_p (rtx, machine_mode, bool, bool);
 extern int arc_return_address_register (unsigned int);
 extern unsigned int arc_compute_function_type (struct function *);
 extern bool arc_is_uncached_mem_p (rtx);
-extern bool arc_lra_p (void);
 extern bool gen_operands_ldd_std (rtx *operands, bool load, bool commute);
+extern bool arc_check_multi (rtx, bool);
 #endif /* RTX_CODE */
 
 extern unsigned int arc_compute_frame_size (int);

gcc/config/arc/arc.md

@@ -6432,6 +6432,182 @@ core_3, archs4x, archs4xd, archs4xd_slow"
    }
 )
 
+(define_insn "*push_multi_fp"
+  [(match_parallel 0 "push_multi_operand"
+		   [(set (reg:SI SP_REG)
+			 (plus:SI (reg:SI SP_REG)
+				  (match_operand 1 "immediate_operand" "")))
+		    (set (mem:SI (plus:SI (reg:SI SP_REG)
+					  (match_dup 1)))
+			 (reg:SI 13))])]
+  "TARGET_CODE_DENSITY"
+  {
+   int len = XVECLEN (operands[0], 0);
+   rtx tmp = XVECEXP (operands[0], 0, len - 1);
+   if (MEM_P (XEXP (tmp, 0)))
+     {
+      operands[2] = XEXP (tmp, 1);
+      return "enter_s\\t{r13-%2} ; sp=sp-%1";
+     }
+   else
+     {
+      tmp = XVECEXP (operands[0], 0, len - 3);
+      operands[2] = XEXP (tmp, 1);
+      return "enter_s\\t{r13-%2, fp} ; sp=sp-%1";
+     }
+  }
+  [(set_attr "type" "call_no_delay_slot")
+   (set_attr "length" "2")])
+
+(define_insn "*push_multi_fp_blink"
+  [(match_parallel 0 "push_multi_operand"
+		   [(set (reg:SI SP_REG)
+			 (plus:SI (reg:SI SP_REG)
+				  (match_operand 1 "immediate_operand" "")))
+		    (set (mem:SI (plus:SI (reg:SI SP_REG)
+					  (match_dup 1)))
+			 (reg:SI RETURN_ADDR_REGNUM))])]
+  "TARGET_CODE_DENSITY"
+  {
+   int len = XVECLEN (operands[0], 0);
+   rtx tmp = XVECEXP (operands[0], 0, len - 1);
+   if (MEM_P (XEXP (tmp, 0)))
+     {
+      operands[2] = XEXP (tmp, 1);
+      return "enter_s\\t{r13-%2, blink} ; sp=sp-%1";
+     }
+   else
+     {
+      tmp = XVECEXP (operands[0], 0, len - 3);
+      operands[2] = XEXP (tmp, 1);
+      return "enter_s\\t{r13-%2, fp, blink} ; sp=sp-%1";
+     }
+  }
+  [(set_attr "type" "call_no_delay_slot")
+   (set_attr "length" "2")])
+
+(define_insn "*pop_multi_fp"
+  [(match_parallel 0 "pop_multi_operand"
+		   [(set (reg:SI SP_REG)
+			 (plus:SI (reg:SI SP_REG)
+				  (match_operand 1 "immediate_operand" "")))
+		    (set (reg:SI 13)
+			 (mem:SI
+			  (plus:SI
+			   (reg:SI SP_REG)
+			   (match_operand 2 "immediate_operand" ""))))])]
+  "TARGET_CODE_DENSITY"
+  {
+   int len = XVECLEN (operands[0], 0);
+   rtx tmp = XVECEXP (operands[0], 0, len - 1);
+   if (XEXP (tmp, 0) != frame_pointer_rtx)
+     {
+      operands[3] = XEXP (tmp, 0);
+      gcc_assert (INTVAL (operands[1]) == INTVAL (operands[2]));
+      return "leave_s\\t{r13-%3} ; sp=sp+%1";
+     }
+   else
+     {
+      tmp = XVECEXP (operands[0], 0, len - 2);
+      operands[3] = XEXP (tmp, 0);
+      return "leave_s\\t{r13-%3, fp} ; sp=sp+%1";
+     }
+  }
+  [(set_attr "type" "call_no_delay_slot")
+   (set_attr "length" "2")])
+
+(define_insn "*pop_multi_fp_blink"
+  [(match_parallel 0 "pop_multi_operand"
+		   [(set (reg:SI SP_REG)
+			 (plus:SI (reg:SI SP_REG)
+				  (match_operand 1 "immediate_operand" "")))
+		    (set (reg:SI RETURN_ADDR_REGNUM)
+			 (mem:SI
+			  (plus:SI
+			   (reg:SI SP_REG)
+			   (match_operand 2 "immediate_operand" ""))))])]
+  "TARGET_CODE_DENSITY"
+  {
+   int len = XVECLEN (operands[0], 0);
+   rtx tmp = XVECEXP (operands[0], 0, len - 1);
+   if (XEXP (tmp, 0) != frame_pointer_rtx)
+     {
+      operands[3] = XEXP (tmp, 0);
+      gcc_assert (INTVAL (operands[1]) == INTVAL (operands[2]));
+      return "leave_s\\t{r13-%3, blink} ; sp=sp+%1";
+     }
+   else
+     {
+      tmp = XVECEXP (operands[0], 0, len - 2);
+      operands[3] = XEXP (tmp, 0);
+      return "leave_s\\t{r13-%3, fp, blink} ; sp=sp+%1";
+     }
+  }
+  [(set_attr "type" "call_no_delay_slot")
+   (set_attr "length" "2")])
+
+(define_insn "*pop_multi_fp_ret"
+  [(match_parallel 0 "pop_multi_operand"
+		   [(return)
+		    (set (reg:SI SP_REG)
+			 (plus:SI (reg:SI SP_REG)
+				  (match_operand 1 "immediate_operand" "")))
+		    (set (reg:SI 13)
+			 (mem:SI
+			  (plus:SI
+			   (reg:SI SP_REG)
+			   (match_operand 2 "immediate_operand" ""))))])]
+  "TARGET_CODE_DENSITY"
+  {
+   int len = XVECLEN (operands[0], 0);
+   rtx tmp = XVECEXP (operands[0], 0, len - 1);
+   if (XEXP (tmp, 0) != frame_pointer_rtx)
+     {
+      operands[3] = XEXP (tmp, 0);
+      gcc_assert (INTVAL (operands[1]) == INTVAL (operands[2]));
+      return "leave_s\\t{r13-%3, pcl} ; sp=sp+%1";
+     }
+   else
+     {
+      tmp = XVECEXP (operands[0], 0, len - 2);
+      operands[3] = XEXP (tmp, 0);
+      return "leave_s\\t{r13-%3, fp, pcl} ; sp=sp+%1";
+     }
+  }
+  [(set_attr "type" "call_no_delay_slot")
+   (set_attr "length" "2")])
+
+(define_insn "*pop_multi_fp_blink_ret"
+  [(match_parallel 0 "pop_multi_operand"
+		   [(return)
+		    (set (reg:SI SP_REG)
+			 (plus:SI (reg:SI SP_REG)
+				  (match_operand 1 "immediate_operand" "")))
+		    (set (reg:SI RETURN_ADDR_REGNUM)
+			 (mem:SI
+			  (plus:SI
+			   (reg:SI SP_REG)
+			   (match_operand 2 "immediate_operand" ""))))])]
+  "TARGET_CODE_DENSITY"
+  {
+   int len = XVECLEN (operands[0], 0);
+   rtx tmp = XVECEXP (operands[0], 0, len - 1);
+   if (XEXP (tmp, 0) != frame_pointer_rtx)
+     {
+      operands[3] = XEXP (tmp, 0);
+      gcc_assert (INTVAL (operands[1]) == INTVAL (operands[2]));
+      return "leave_s\\t{r13-%3, blink, pcl} ; sp=sp+%1";
+     }
+   else
+     {
+      tmp = XVECEXP (operands[0], 0, len - 2);
+      operands[3] = XEXP (tmp, 0);
+      return "leave_s\\t{r13-%3, fp, blink, pcl} ; sp=sp+%1";
+     }
+  }
+  [(set_attr "type" "call_no_delay_slot")
+   (set_attr "length" "2")])
+
 ;; include the arc-FPX instructions
 (include "fpx.md")
 

gcc/config/arc/arc.opt

@@ -193,9 +193,9 @@ msdata
 Target Report InverseMask(NO_SDATA_SET)
 Generate sdata references.  This is the default, unless you compile for PIC.
 
-mno-millicode
-Target Report Mask(NO_MILLICODE_THUNK_SET)
-Do not generate millicode thunks (needed only with -Os).
+mmillicode
+Target Report Mask(MILLICODE_THUNK_SET)
+Generate millicode thunks.
 
 mspfp
 Target Report Mask(SPFP_COMPACT_SET)
@@ -538,3 +538,7 @@ Enable 16-entry register file.
 mbranch-index
 Target Report Var(TARGET_BRANCH_INDEX) Init(DEFAULT_BRANCH_INDEX)
 Enable use of BI/BIH instructions when available.
+
+mcode-density-frame
+Target Report Var(TARGET_CODE_DENSITY_FRAME)
+Enable ENTER_S and LEAVE_S opcodes for ARCv2.

gcc/config/arc/predicates.md

@@ -800,3 +800,15 @@
 (define_predicate "arc_short_operand"
   (ior (match_test "register_operand (op, mode)")
        (match_test "short_unsigned_const_operand (op, mode)")))
+
+(define_special_predicate "push_multi_operand"
+  (match_code "parallel")
+  {
+   return arc_check_multi (op, true);
+})
+
+(define_special_predicate "pop_multi_operand"
+  (match_code "parallel")
+  {
+   return arc_check_multi (op, false);
+})

gcc/doc/invoke.texi

@@ -651,9 +651,9 @@ Objective-C and Objective-C++ Dialects}.
 -malign-call  -mauto-modify-reg  -mbbit-peephole  -mno-brcc @gol
 -mcase-vector-pcrel  -mcompact-casesi  -mno-cond-exec  -mearly-cbranchsi @gol
 -mexpand-adddi  -mindexed-loads  -mlra  -mlra-priority-none @gol
--mlra-priority-compact mlra-priority-noncompact  -mno-millicode @gol
+-mlra-priority-compact mlra-priority-noncompact  -mmillicode @gol
 -mmixed-code  -mq-class  -mRcq  -mRcw  -msize-level=@var{level} @gol
--mtune=@var{cpu}  -mmultcost=@var{num} @gol
+-mtune=@var{cpu}  -mmultcost=@var{num} -mcode-density-frame @gol
 -munalign-prob-threshold=@var{probability}  -mmpy-option=@var{multo} @gol
 -mdiv-rem  -mcode-density  -mll64  -mfpu=@var{fpu} -mrf16  -mbranch-index}
 
@@ -16229,15 +16229,21 @@ Indicate target register priority for r0..r3 / r12..r15.
 @opindex mlra-priority-noncompact
 Reduce target register priority for r0..r3 / r12..r15.
 
-@item -mno-millicode
-@opindex mno-millicode
+@item -mmillicode
+@opindex mmillicode
 When optimizing for size (using @option{-Os}), prologues and epilogues
 that have to save or restore a large number of registers are often
 shortened by using call to a special function in libgcc; this is
 referred to as a @emph{millicode} call.  As these calls can pose
 performance issues, and/or cause linking issues when linking in a
-nonstandard way, this option is provided to turn off millicode call
-generation.
+nonstandard way, this option is provided to turn on or off millicode
+call generation.
+
+@item -mcode-density-frame
+@opindex mcode-density-frame
+This option enable the compiler to emit @code{enter} and @code{leave}
+instructions.  These instructions are only valid for CPUs with
+code-density feature.
 
 @item -mmixed-code
 @opindex mmixed-code

gcc/testsuite/ChangeLog

+2018-11-13  Claudiu Zissulescu  <claziss@synopsys.com>
+
+	* gcc.target/arc/firq-1.c: Update test.
+	* gcc.target/arc/firq-3.c: Likewise.
+	* gcc.target/arc/firq-4.c: Likewise.
+	* gcc.target/arc/interrupt-6.c: Likewise.
+
 2018-11-13  Jakub Jelinek  <jakub@redhat.com>
 
 	PR rtl-optimization/87918

gcc/testsuite/gcc.target/arc/firq-1.c

@@ -20,8 +20,8 @@ handler1 (void)
        : "r0", "r1", "r2", "r3", "r4",
 	 "r5", "r6", "r7", "r8", "r9");
 }
-/* { dg-final { scan-assembler-times "r2,\\\[sp,\[0-9\]+\\\]" 2 } } */
-/* { dg-final { scan-assembler-times "r4,\\\[sp,\[0-9\]+\\\]" 2 } } */
-/* { dg-final { scan-assembler-times "r6,\\\[sp,\[0-9\]+\\\]" 2 } } */
-/* { dg-final { scan-assembler-times "r8,\\\[sp,\[0-9\]+\\\]" 2 } } */
+/* { dg-final { scan-assembler-times "r2,\\\[sp" 2 } } */
+/* { dg-final { scan-assembler-times "r4,\\\[sp" 2 } } */
+/* { dg-final { scan-assembler-times "r6,\\\[sp" 2 } } */
+/* { dg-final { scan-assembler-times "r8,\\\[sp" 2 } } */
 /* { dg-final { scan-assembler "rtie" } } */

gcc/testsuite/gcc.target/arc/firq-3.c

@@ -28,13 +28,13 @@ handler1 (void)
 /* { dg-final { scan-assembler-not "r15,\\\[sp" } } */
 
 /* { dg-final { scan-assembler-times "r4,\\\[sp" 2 } } */
-/* { dg-final { scan-assembler-times "r6,\\\[sp,\[0-9\]+\\\]" 2 } } */
-/* { dg-final { scan-assembler-times "r8,\\\[sp,\[0-9\]+\\\]" 2 } } */
-/* { dg-final { scan-assembler-times "r10,\\\[sp,\[0-9\]+\\\]" 2 } } */
-/* { dg-final { scan-assembler-times "r16,\\\[sp,\[0-9\]+\\\]" 2 } } */
-/* { dg-final { scan-assembler-times "r18,\\\[sp,\[0-9\]+\\\]" 2 } } */
-/* { dg-final { scan-assembler-times "r20,\\\[sp,\[0-9\]+\\\]" 2 } } */
-/* { dg-final { scan-assembler-times "r24,\\\[sp,\[0-9\]+\\\]" 2 } } */
+/* { dg-final { scan-assembler-times "r6,\\\[sp" 2 } } */
+/* { dg-final { scan-assembler-times "r8,\\\[sp" 2 } } */
+/* { dg-final { scan-assembler-times "r10,\\\[sp" 2 } } */
+/* { dg-final { scan-assembler-times "r16,\\\[sp" 2 } } */
+/* { dg-final { scan-assembler-times "r18,\\\[sp" 2 } } */
+/* { dg-final { scan-assembler-times "r20,\\\[sp" 2 } } */
+/* { dg-final { scan-assembler-times "r24,\\\[sp" 2 } } */
 /* { dg-final { scan-assembler-times "fp,\\\[sp," 2 } } */
 
 /* { dg-final { scan-assembler "rtie" } } */

gcc/testsuite/gcc.target/arc/firq-4.c

@@ -18,13 +18,13 @@ handler1 (void)
 		  "r25", "fp");
 }
 /* { dg-final { scan-assembler-times "r4,\\\[sp" 2 } } */
-/* { dg-final { scan-assembler-times "r6,\\\[sp,\[0-9\]+\\\]" 2 } } */
-/* { dg-final { scan-assembler-times "r8,\\\[sp,\[0-9\]+\\\]" 2 } } */
+/* { dg-final { scan-assembler-times "r6,\\\[sp" 2 } } */
+/* { dg-final { scan-assembler-times "r8,\\\[sp" 2 } } */
 
-/* { dg-final { scan-assembler-times "r16,\\\[sp,\[0-9\]+\\\]" 2 } } */
-/* { dg-final { scan-assembler-times "r18,\\\[sp,\[0-9\]+\\\]" 2 } } */
-/* { dg-final { scan-assembler-times "r20,\\\[sp,\[0-9\]+\\\]" 2 } } */
-/* { dg-final { scan-assembler-times "r24,\\\[sp,\[0-9\]+\\\]" 2 } } */
+/* { dg-final { scan-assembler-times "r16,\\\[sp" 2 } } */
+/* { dg-final { scan-assembler-times "r18,\\\[sp" 2 } } */
+/* { dg-final { scan-assembler-times "r20,\\\[sp" 2 } } */
+/* { dg-final { scan-assembler-times "r24,\\\[sp" 2 } } */
 
 /* { dg-final { scan-assembler-not "fp,\\\[sp" } } */
 /* { dg-final { scan-assembler-not "push.*fp" } } */

gcc/testsuite/gcc.target/arc/interrupt-6.c

@@ -18,5 +18,5 @@ foo(void)
   bar (p);
 }
 /* { dg-final { scan-assembler-not ".*fp,\\\[sp" } } */
-/* { dg-final { scan-assembler "ld.*blink,\\\[sp\\\]" } } */
+/* { dg-final { scan-assembler "ld.*blink,\\\[sp" } } */
 /* { dg-final { scan-assembler "push_s.*blink" } } */