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riscv-gcc-1
Commit 8f5d6855 by Richard Henderson Committed by Richard Henderson
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alpha.md (addsi3, subsi3): Expand to a DImode temporary so as to expose this midpoint to CSE. 

        * alpha.md (addsi3, subsi3): Expand to a DImode temporary so as
        to expose this midpoint to CSE.

From-SVN: r23536
parent 4ba687c8
Showing with 15 additions and 8 deletions
gcc/ChangeLog
Thu Nov 5 03:29:19 1998 Richard Henderson <rth@cygnus.com>
* alpha.md (addsi3, subsi3): Expand to a DImode temporary so as
to expose this midpoint to CSE.
Thu Nov 5 03:42:54 1998 David S. Miller <davem@pierdol.cobaltmicro.com> Thu Nov 5 03:42:54 1998 David S. Miller <davem@pierdol.cobaltmicro.com>
* config/sparc/sparc.md (movdf_const_intreg_sp64): Enable again. * config/sparc/sparc.md (movdf_const_intreg_sp64): Enable again.
......
gcc/config/alpha/alpha.md
...@@ -426,10 +426,11 @@ ...@@ -426,10 +426,11 @@
(match_operand:SI 2 "add_operand" "")))] (match_operand:SI 2 "add_operand" "")))]
"" ""
" "
{ emit_insn (gen_rtx_SET (VOIDmode, gen_lowpart (DImode, operands[0]), {
gen_rtx_PLUS (DImode, rtx tmp = gen_reg_rtx (DImode);
gen_lowpart (DImode, operands[1]), emit_insn (gen_adddi3 (tmp, gen_lowpart (DImode, operands[1]),
gen_lowpart (DImode, operands[2])))); gen_lowpart (DImode, operands[2])));
emit_move_insn (operands[0], gen_lowpart (SImode, tmp));
DONE; DONE;
} ") } ")
...@@ -712,10 +713,11 @@ ...@@ -712,10 +713,11 @@
(match_operand:SI 2 "reg_or_8bit_operand" "")))] (match_operand:SI 2 "reg_or_8bit_operand" "")))]
"" ""
" "
{ emit_insn (gen_rtx_SET (VOIDmode, gen_lowpart (DImode, operands[0]), {
gen_rtx_MINUS (DImode, rtx tmp = gen_reg_rtx (DImode);
gen_lowpart (DImode, operands[1]), emit_insn (gen_subdi3 (tmp, gen_lowpart (DImode, operands[1]),
gen_lowpart (DImode, operands[2])))); gen_lowpart (DImode, operands[2])));
emit_move_insn (operands[0], gen_lowpart (SImode, tmp));
DONE; DONE;
} ") } ")
......
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