Revert [ARM] Remove neon-testgen.ml and generated tests.

From-SVN: r230296

gcc/ChangeLog

+2015-11-13  Christophe Lyon  <christophe.lyon@linaro.org>
+
+	Revert [ARM] Remove neon-testgen.ml and generated tests.
+
+	2015-11-12  Christophe Lyon  <christophe.lyon@linaro.org>
+
+	[ARM] Remove neon-testgen.ml and generated tests.
+
+	* config/arm/neon-testgen.ml: Remove.
+
 2015-11-13  Richard Biener  <rguenther@suse.de>
 
 	* tree-vect-loop.c (vect_analyze_loop_2): Add fatal parameter.

gcc/testsuite/gcc.target/arm/neon/vRaddhns16.c

+/* Test the `vRaddhns16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vRaddhns16 (void)
+{
+  int8x8_t out_int8x8_t;
+  int16x8_t arg0_int16x8_t;
+  int16x8_t arg1_int16x8_t;
+
+  out_int8x8_t = vraddhn_s16 (arg0_int16x8_t, arg1_int16x8_t);
+}
+
+/* { dg-final { scan-assembler "vraddhn\.i16\[ 	\]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */

gcc/testsuite/gcc.target/arm/neon/vRaddhns32.c

+/* Test the `vRaddhns32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vRaddhns32 (void)
+{
+  int16x4_t out_int16x4_t;
+  int32x4_t arg0_int32x4_t;
+  int32x4_t arg1_int32x4_t;
+
+  out_int16x4_t = vraddhn_s32 (arg0_int32x4_t, arg1_int32x4_t);
+}
+
+/* { dg-final { scan-assembler "vraddhn\.i32\[ 	\]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */

gcc/testsuite/gcc.target/arm/neon/vRaddhns64.c

+/* Test the `vRaddhns64' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vRaddhns64 (void)
+{
+  int32x2_t out_int32x2_t;
+  int64x2_t arg0_int64x2_t;
+  int64x2_t arg1_int64x2_t;
+
+  out_int32x2_t = vraddhn_s64 (arg0_int64x2_t, arg1_int64x2_t);
+}
+
+/* { dg-final { scan-assembler "vraddhn\.i64\[ 	\]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */

gcc/testsuite/gcc.target/arm/neon/vRaddhnu16.c

+/* Test the `vRaddhnu16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vRaddhnu16 (void)
+{
+  uint8x8_t out_uint8x8_t;
+  uint16x8_t arg0_uint16x8_t;
+  uint16x8_t arg1_uint16x8_t;
+
+  out_uint8x8_t = vraddhn_u16 (arg0_uint16x8_t, arg1_uint16x8_t);
+}
+
+/* { dg-final { scan-assembler "vraddhn\.i16\[ 	\]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */

gcc/testsuite/gcc.target/arm/neon/vRaddhnu32.c

+/* Test the `vRaddhnu32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vRaddhnu32 (void)
+{
+  uint16x4_t out_uint16x4_t;
+  uint32x4_t arg0_uint32x4_t;
+  uint32x4_t arg1_uint32x4_t;
+
+  out_uint16x4_t = vraddhn_u32 (arg0_uint32x4_t, arg1_uint32x4_t);
+}
+
+/* { dg-final { scan-assembler "vraddhn\.i32\[ 	\]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */

gcc/testsuite/gcc.target/arm/neon/vRaddhnu64.c

+/* Test the `vRaddhnu64' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vRaddhnu64 (void)
+{
+  uint32x2_t out_uint32x2_t;
+  uint64x2_t arg0_uint64x2_t;
+  uint64x2_t arg1_uint64x2_t;
+
+  out_uint32x2_t = vraddhn_u64 (arg0_uint64x2_t, arg1_uint64x2_t);
+}
+
+/* { dg-final { scan-assembler "vraddhn\.i64\[ 	\]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */

gcc/testsuite/gcc.target/arm/neon/vRhaddQs16.c

+/* Test the `vRhaddQs16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vRhaddQs16 (void)
+{
+  int16x8_t out_int16x8_t;
+  int16x8_t arg0_int16x8_t;
+  int16x8_t arg1_int16x8_t;
+
+  out_int16x8_t = vrhaddq_s16 (arg0_int16x8_t, arg1_int16x8_t);
+}
+
+/* { dg-final { scan-assembler "vrhadd\.s16\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */

gcc/testsuite/gcc.target/arm/neon/vRhaddQs32.c

+/* Test the `vRhaddQs32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vRhaddQs32 (void)
+{
+  int32x4_t out_int32x4_t;
+  int32x4_t arg0_int32x4_t;
+  int32x4_t arg1_int32x4_t;
+
+  out_int32x4_t = vrhaddq_s32 (arg0_int32x4_t, arg1_int32x4_t);
+}
+
+/* { dg-final { scan-assembler "vrhadd\.s32\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */

gcc/testsuite/gcc.target/arm/neon/vRhaddQs8.c

+/* Test the `vRhaddQs8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vRhaddQs8 (void)
+{
+  int8x16_t out_int8x16_t;
+  int8x16_t arg0_int8x16_t;
+  int8x16_t arg1_int8x16_t;
+
+  out_int8x16_t = vrhaddq_s8 (arg0_int8x16_t, arg1_int8x16_t);
+}
+
+/* { dg-final { scan-assembler "vrhadd\.s8\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */

gcc/testsuite/gcc.target/arm/neon/vRhaddQu16.c

+/* Test the `vRhaddQu16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vRhaddQu16 (void)
+{
+  uint16x8_t out_uint16x8_t;
+  uint16x8_t arg0_uint16x8_t;
+  uint16x8_t arg1_uint16x8_t;
+
+  out_uint16x8_t = vrhaddq_u16 (arg0_uint16x8_t, arg1_uint16x8_t);
+}
+
+/* { dg-final { scan-assembler "vrhadd\.u16\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */

gcc/testsuite/gcc.target/arm/neon/vRhaddQu32.c

+/* Test the `vRhaddQu32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vRhaddQu32 (void)
+{
+  uint32x4_t out_uint32x4_t;
+  uint32x4_t arg0_uint32x4_t;
+  uint32x4_t arg1_uint32x4_t;
+
+  out_uint32x4_t = vrhaddq_u32 (arg0_uint32x4_t, arg1_uint32x4_t);
+}
+
+/* { dg-final { scan-assembler "vrhadd\.u32\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */

gcc/testsuite/gcc.target/arm/neon/vRhaddQu8.c

+/* Test the `vRhaddQu8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vRhaddQu8 (void)
+{
+  uint8x16_t out_uint8x16_t;
+  uint8x16_t arg0_uint8x16_t;
+  uint8x16_t arg1_uint8x16_t;
+
+  out_uint8x16_t = vrhaddq_u8 (arg0_uint8x16_t, arg1_uint8x16_t);
+}
+
+/* { dg-final { scan-assembler "vrhadd\.u8\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */

gcc/testsuite/gcc.target/arm/neon/vRhadds16.c

+/* Test the `vRhadds16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vRhadds16 (void)
+{
+  int16x4_t out_int16x4_t;
+  int16x4_t arg0_int16x4_t;
+  int16x4_t arg1_int16x4_t;
+
+  out_int16x4_t = vrhadd_s16 (arg0_int16x4_t, arg1_int16x4_t);
+}
+
+/* { dg-final { scan-assembler "vrhadd\.s16\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */

gcc/testsuite/gcc.target/arm/neon/vRhadds32.c

+/* Test the `vRhadds32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vRhadds32 (void)
+{
+  int32x2_t out_int32x2_t;
+  int32x2_t arg0_int32x2_t;
+  int32x2_t arg1_int32x2_t;
+
+  out_int32x2_t = vrhadd_s32 (arg0_int32x2_t, arg1_int32x2_t);
+}
+
+/* { dg-final { scan-assembler "vrhadd\.s32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */

gcc/testsuite/gcc.target/arm/neon/vRhadds8.c

+/* Test the `vRhadds8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vRhadds8 (void)
+{
+  int8x8_t out_int8x8_t;
+  int8x8_t arg0_int8x8_t;
+  int8x8_t arg1_int8x8_t;
+
+  out_int8x8_t = vrhadd_s8 (arg0_int8x8_t, arg1_int8x8_t);
+}
+
+/* { dg-final { scan-assembler "vrhadd\.s8\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */

gcc/testsuite/gcc.target/arm/neon/vRhaddu16.c

+/* Test the `vRhaddu16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vRhaddu16 (void)
+{
+  uint16x4_t out_uint16x4_t;
+  uint16x4_t arg0_uint16x4_t;
+  uint16x4_t arg1_uint16x4_t;
+
+  out_uint16x4_t = vrhadd_u16 (arg0_uint16x4_t, arg1_uint16x4_t);
+}
+
+/* { dg-final { scan-assembler "vrhadd\.u16\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */

gcc/testsuite/gcc.target/arm/neon/vRhaddu32.c

+/* Test the `vRhaddu32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vRhaddu32 (void)
+{
+  uint32x2_t out_uint32x2_t;
+  uint32x2_t arg0_uint32x2_t;
+  uint32x2_t arg1_uint32x2_t;
+
+  out_uint32x2_t = vrhadd_u32 (arg0_uint32x2_t, arg1_uint32x2_t);
+}
+
+/* { dg-final { scan-assembler "vrhadd\.u32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */

gcc/testsuite/gcc.target/arm/neon/vRhaddu8.c

+/* Test the `vRhaddu8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vRhaddu8 (void)
+{
+  uint8x8_t out_uint8x8_t;
+  uint8x8_t arg0_uint8x8_t;
+  uint8x8_t arg1_uint8x8_t;
+
+  out_uint8x8_t = vrhadd_u8 (arg0_uint8x8_t, arg1_uint8x8_t);
+}
+
+/* { dg-final { scan-assembler "vrhadd\.u8\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */

gcc/testsuite/gcc.target/arm/neon/vRshlQs16.c

+/* Test the `vRshlQs16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vRshlQs16 (void)
+{
+  int16x8_t out_int16x8_t;
+  int16x8_t arg0_int16x8_t;
+  int16x8_t arg1_int16x8_t;
+
+  out_int16x8_t = vrshlq_s16 (arg0_int16x8_t, arg1_int16x8_t);
+}
+
+/* { dg-final { scan-assembler "vrshl\.s16\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */

gcc/testsuite/gcc.target/arm/neon/vRshlQs32.c

+/* Test the `vRshlQs32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vRshlQs32 (void)
+{
+  int32x4_t out_int32x4_t;
+  int32x4_t arg0_int32x4_t;
+  int32x4_t arg1_int32x4_t;
+
+  out_int32x4_t = vrshlq_s32 (arg0_int32x4_t, arg1_int32x4_t);
+}
+
+/* { dg-final { scan-assembler "vrshl\.s32\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */

gcc/testsuite/gcc.target/arm/neon/vRshlQs64.c

+/* Test the `vRshlQs64' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vRshlQs64 (void)
+{
+  int64x2_t out_int64x2_t;
+  int64x2_t arg0_int64x2_t;
+  int64x2_t arg1_int64x2_t;
+
+  out_int64x2_t = vrshlq_s64 (arg0_int64x2_t, arg1_int64x2_t);
+}
+
+/* { dg-final { scan-assembler "vrshl\.s64\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */

gcc/testsuite/gcc.target/arm/neon/vRshlQs8.c

+/* Test the `vRshlQs8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vRshlQs8 (void)
+{
+  int8x16_t out_int8x16_t;
+  int8x16_t arg0_int8x16_t;
+  int8x16_t arg1_int8x16_t;
+
+  out_int8x16_t = vrshlq_s8 (arg0_int8x16_t, arg1_int8x16_t);
+}
+
+/* { dg-final { scan-assembler "vrshl\.s8\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */

gcc/testsuite/gcc.target/arm/neon/vRshlQu16.c

+/* Test the `vRshlQu16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vRshlQu16 (void)
+{
+  uint16x8_t out_uint16x8_t;
+  uint16x8_t arg0_uint16x8_t;
+  int16x8_t arg1_int16x8_t;
+
+  out_uint16x8_t = vrshlq_u16 (arg0_uint16x8_t, arg1_int16x8_t);
+}
+
+/* { dg-final { scan-assembler "vrshl\.u16\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */

gcc/testsuite/gcc.target/arm/neon/vRshlQu32.c

+/* Test the `vRshlQu32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vRshlQu32 (void)
+{
+  uint32x4_t out_uint32x4_t;
+  uint32x4_t arg0_uint32x4_t;
+  int32x4_t arg1_int32x4_t;
+
+  out_uint32x4_t = vrshlq_u32 (arg0_uint32x4_t, arg1_int32x4_t);
+}
+
+/* { dg-final { scan-assembler "vrshl\.u32\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */

gcc/testsuite/gcc.target/arm/neon/vRshlQu64.c

+/* Test the `vRshlQu64' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vRshlQu64 (void)
+{
+  uint64x2_t out_uint64x2_t;
+  uint64x2_t arg0_uint64x2_t;
+  int64x2_t arg1_int64x2_t;
+
+  out_uint64x2_t = vrshlq_u64 (arg0_uint64x2_t, arg1_int64x2_t);
+}
+
+/* { dg-final { scan-assembler "vrshl\.u64\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */

gcc/testsuite/gcc.target/arm/neon/vRshlQu8.c

+/* Test the `vRshlQu8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vRshlQu8 (void)
+{
+  uint8x16_t out_uint8x16_t;
+  uint8x16_t arg0_uint8x16_t;
+  int8x16_t arg1_int8x16_t;
+
+  out_uint8x16_t = vrshlq_u8 (arg0_uint8x16_t, arg1_int8x16_t);
+}
+
+/* { dg-final { scan-assembler "vrshl\.u8\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */

gcc/testsuite/gcc.target/arm/neon/vRshls16.c

+/* Test the `vRshls16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vRshls16 (void)
+{
+  int16x4_t out_int16x4_t;
+  int16x4_t arg0_int16x4_t;
+  int16x4_t arg1_int16x4_t;
+
+  out_int16x4_t = vrshl_s16 (arg0_int16x4_t, arg1_int16x4_t);
+}
+
+/* { dg-final { scan-assembler "vrshl\.s16\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */

gcc/testsuite/gcc.target/arm/neon/vRshls32.c

+/* Test the `vRshls32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vRshls32 (void)
+{
+  int32x2_t out_int32x2_t;
+  int32x2_t arg0_int32x2_t;
+  int32x2_t arg1_int32x2_t;
+
+  out_int32x2_t = vrshl_s32 (arg0_int32x2_t, arg1_int32x2_t);
+}
+
+/* { dg-final { scan-assembler "vrshl\.s32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */

gcc/testsuite/gcc.target/arm/neon/vRshls64.c

+/* Test the `vRshls64' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vRshls64 (void)
+{
+  int64x1_t out_int64x1_t;
+  int64x1_t arg0_int64x1_t;
+  int64x1_t arg1_int64x1_t;
+
+  out_int64x1_t = vrshl_s64 (arg0_int64x1_t, arg1_int64x1_t);
+}
+
+/* { dg-final { scan-assembler "vrshl\.s64\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */

gcc/testsuite/gcc.target/arm/neon/vRshls8.c

+/* Test the `vRshls8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vRshls8 (void)
+{
+  int8x8_t out_int8x8_t;
+  int8x8_t arg0_int8x8_t;
+  int8x8_t arg1_int8x8_t;
+
+  out_int8x8_t = vrshl_s8 (arg0_int8x8_t, arg1_int8x8_t);
+}
+
+/* { dg-final { scan-assembler "vrshl\.s8\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */

gcc/testsuite/gcc.target/arm/neon/vRshlu16.c

+/* Test the `vRshlu16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vRshlu16 (void)
+{
+  uint16x4_t out_uint16x4_t;
+  uint16x4_t arg0_uint16x4_t;
+  int16x4_t arg1_int16x4_t;
+
+  out_uint16x4_t = vrshl_u16 (arg0_uint16x4_t, arg1_int16x4_t);
+}
+
+/* { dg-final { scan-assembler "vrshl\.u16\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */

gcc/testsuite/gcc.target/arm/neon/vRshlu32.c

+/* Test the `vRshlu32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vRshlu32 (void)
+{
+  uint32x2_t out_uint32x2_t;
+  uint32x2_t arg0_uint32x2_t;
+  int32x2_t arg1_int32x2_t;
+
+  out_uint32x2_t = vrshl_u32 (arg0_uint32x2_t, arg1_int32x2_t);
+}
+
+/* { dg-final { scan-assembler "vrshl\.u32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */

gcc/testsuite/gcc.target/arm/neon/vRshlu64.c

+/* Test the `vRshlu64' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vRshlu64 (void)
+{
+  uint64x1_t out_uint64x1_t;
+  uint64x1_t arg0_uint64x1_t;
+  int64x1_t arg1_int64x1_t;
+
+  out_uint64x1_t = vrshl_u64 (arg0_uint64x1_t, arg1_int64x1_t);
+}
+
+/* { dg-final { scan-assembler "vrshl\.u64\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */

gcc/testsuite/gcc.target/arm/neon/vRshlu8.c

+/* Test the `vRshlu8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vRshlu8 (void)
+{
+  uint8x8_t out_uint8x8_t;
+  uint8x8_t arg0_uint8x8_t;
+  int8x8_t arg1_int8x8_t;
+
+  out_uint8x8_t = vrshl_u8 (arg0_uint8x8_t, arg1_int8x8_t);
+}
+
+/* { dg-final { scan-assembler "vrshl\.u8\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */

gcc/testsuite/gcc.target/arm/neon/vRshrQ_ns16.c

+/* Test the `vRshrQ_ns16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vRshrQ_ns16 (void)
+{
+  int16x8_t out_int16x8_t;
+  int16x8_t arg0_int16x8_t;
+
+  out_int16x8_t = vrshrq_n_s16 (arg0_int16x8_t, 1);
+}
+
+/* { dg-final { scan-assembler "vrshr\.s16\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */

gcc/testsuite/gcc.target/arm/neon/vRshrQ_ns32.c

+/* Test the `vRshrQ_ns32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vRshrQ_ns32 (void)
+{
+  int32x4_t out_int32x4_t;
+  int32x4_t arg0_int32x4_t;
+
+  out_int32x4_t = vrshrq_n_s32 (arg0_int32x4_t, 1);
+}
+
+/* { dg-final { scan-assembler "vrshr\.s32\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */

gcc/testsuite/gcc.target/arm/neon/vRshrQ_ns64.c

+/* Test the `vRshrQ_ns64' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vRshrQ_ns64 (void)
+{
+  int64x2_t out_int64x2_t;
+  int64x2_t arg0_int64x2_t;
+
+  out_int64x2_t = vrshrq_n_s64 (arg0_int64x2_t, 1);
+}
+
+/* { dg-final { scan-assembler "vrshr\.s64\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */

gcc/testsuite/gcc.target/arm/neon/vRshrQ_ns8.c

+/* Test the `vRshrQ_ns8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vRshrQ_ns8 (void)
+{
+  int8x16_t out_int8x16_t;
+  int8x16_t arg0_int8x16_t;
+
+  out_int8x16_t = vrshrq_n_s8 (arg0_int8x16_t, 1);
+}
+
+/* { dg-final { scan-assembler "vrshr\.s8\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */

gcc/testsuite/gcc.target/arm/neon/vRshrQ_nu16.c

+/* Test the `vRshrQ_nu16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vRshrQ_nu16 (void)
+{
+  uint16x8_t out_uint16x8_t;
+  uint16x8_t arg0_uint16x8_t;
+
+  out_uint16x8_t = vrshrq_n_u16 (arg0_uint16x8_t, 1);
+}
+
+/* { dg-final { scan-assembler "vrshr\.u16\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */

gcc/testsuite/gcc.target/arm/neon/vRshrQ_nu32.c

+/* Test the `vRshrQ_nu32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vRshrQ_nu32 (void)
+{
+  uint32x4_t out_uint32x4_t;
+  uint32x4_t arg0_uint32x4_t;
+
+  out_uint32x4_t = vrshrq_n_u32 (arg0_uint32x4_t, 1);
+}
+
+/* { dg-final { scan-assembler "vrshr\.u32\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */

gcc/testsuite/gcc.target/arm/neon/vRshrQ_nu64.c

+/* Test the `vRshrQ_nu64' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vRshrQ_nu64 (void)
+{
+  uint64x2_t out_uint64x2_t;
+  uint64x2_t arg0_uint64x2_t;
+
+  out_uint64x2_t = vrshrq_n_u64 (arg0_uint64x2_t, 1);
+}
+
+/* { dg-final { scan-assembler "vrshr\.u64\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */

gcc/testsuite/gcc.target/arm/neon/vRshrQ_nu8.c

+/* Test the `vRshrQ_nu8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vRshrQ_nu8 (void)
+{
+  uint8x16_t out_uint8x16_t;
+  uint8x16_t arg0_uint8x16_t;
+
+  out_uint8x16_t = vrshrq_n_u8 (arg0_uint8x16_t, 1);
+}
+
+/* { dg-final { scan-assembler "vrshr\.u8\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */

gcc/testsuite/gcc.target/arm/neon/vRshr_ns16.c

+/* Test the `vRshr_ns16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vRshr_ns16 (void)
+{
+  int16x4_t out_int16x4_t;
+  int16x4_t arg0_int16x4_t;
+
+  out_int16x4_t = vrshr_n_s16 (arg0_int16x4_t, 1);
+}
+
+/* { dg-final { scan-assembler "vrshr\.s16\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */

gcc/testsuite/gcc.target/arm/neon/vRshr_ns32.c

+/* Test the `vRshr_ns32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vRshr_ns32 (void)
+{
+  int32x2_t out_int32x2_t;
+  int32x2_t arg0_int32x2_t;
+
+  out_int32x2_t = vrshr_n_s32 (arg0_int32x2_t, 1);
+}
+
+/* { dg-final { scan-assembler "vrshr\.s32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */

gcc/testsuite/gcc.target/arm/neon/vRshr_ns64.c

+/* Test the `vRshr_ns64' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vRshr_ns64 (void)
+{
+  int64x1_t out_int64x1_t;
+  int64x1_t arg0_int64x1_t;
+
+  out_int64x1_t = vrshr_n_s64 (arg0_int64x1_t, 1);
+}
+
+/* { dg-final { scan-assembler "vrshr\.s64\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */

gcc/testsuite/gcc.target/arm/neon/vRshr_ns8.c

+/* Test the `vRshr_ns8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vRshr_ns8 (void)
+{
+  int8x8_t out_int8x8_t;
+  int8x8_t arg0_int8x8_t;
+
+  out_int8x8_t = vrshr_n_s8 (arg0_int8x8_t, 1);
+}
+
+/* { dg-final { scan-assembler "vrshr\.s8\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */

gcc/testsuite/gcc.target/arm/neon/vRshr_nu16.c

+/* Test the `vRshr_nu16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vRshr_nu16 (void)
+{
+  uint16x4_t out_uint16x4_t;
+  uint16x4_t arg0_uint16x4_t;
+
+  out_uint16x4_t = vrshr_n_u16 (arg0_uint16x4_t, 1);
+}
+
+/* { dg-final { scan-assembler "vrshr\.u16\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */

gcc/testsuite/gcc.target/arm/neon/vRshr_nu32.c

+/* Test the `vRshr_nu32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vRshr_nu32 (void)
+{
+  uint32x2_t out_uint32x2_t;
+  uint32x2_t arg0_uint32x2_t;
+
+  out_uint32x2_t = vrshr_n_u32 (arg0_uint32x2_t, 1);
+}
+
+/* { dg-final { scan-assembler "vrshr\.u32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */

gcc/testsuite/gcc.target/arm/neon/vRshr_nu64.c

+/* Test the `vRshr_nu64' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vRshr_nu64 (void)
+{
+  uint64x1_t out_uint64x1_t;
+  uint64x1_t arg0_uint64x1_t;
+
+  out_uint64x1_t = vrshr_n_u64 (arg0_uint64x1_t, 1);
+}
+
+/* { dg-final { scan-assembler "vrshr\.u64\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */

gcc/testsuite/gcc.target/arm/neon/vRshr_nu8.c

+/* Test the `vRshr_nu8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vRshr_nu8 (void)
+{
+  uint8x8_t out_uint8x8_t;
+  uint8x8_t arg0_uint8x8_t;
+
+  out_uint8x8_t = vrshr_n_u8 (arg0_uint8x8_t, 1);
+}
+
+/* { dg-final { scan-assembler "vrshr\.u8\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */

gcc/testsuite/gcc.target/arm/neon/vRshrn_ns16.c

+/* Test the `vRshrn_ns16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vRshrn_ns16 (void)
+{
+  int8x8_t out_int8x8_t;
+  int16x8_t arg0_int16x8_t;
+
+  out_int8x8_t = vrshrn_n_s16 (arg0_int16x8_t, 1);
+}
+
+/* { dg-final { scan-assembler "vrshrn\.i16\[ 	\]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */

gcc/testsuite/gcc.target/arm/neon/vRshrn_ns32.c

+/* Test the `vRshrn_ns32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vRshrn_ns32 (void)
+{
+  int16x4_t out_int16x4_t;
+  int32x4_t arg0_int32x4_t;
+
+  out_int16x4_t = vrshrn_n_s32 (arg0_int32x4_t, 1);
+}
+
+/* { dg-final { scan-assembler "vrshrn\.i32\[ 	\]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */

gcc/testsuite/gcc.target/arm/neon/vRshrn_ns64.c

+/* Test the `vRshrn_ns64' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vRshrn_ns64 (void)
+{
+  int32x2_t out_int32x2_t;
+  int64x2_t arg0_int64x2_t;
+
+  out_int32x2_t = vrshrn_n_s64 (arg0_int64x2_t, 1);
+}
+
+/* { dg-final { scan-assembler "vrshrn\.i64\[ 	\]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */

gcc/testsuite/gcc.target/arm/neon/vRshrn_nu16.c

+/* Test the `vRshrn_nu16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vRshrn_nu16 (void)
+{
+  uint8x8_t out_uint8x8_t;
+  uint16x8_t arg0_uint16x8_t;
+
+  out_uint8x8_t = vrshrn_n_u16 (arg0_uint16x8_t, 1);
+}
+
+/* { dg-final { scan-assembler "vrshrn\.i16\[ 	\]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */

gcc/testsuite/gcc.target/arm/neon/vRshrn_nu32.c

+/* Test the `vRshrn_nu32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vRshrn_nu32 (void)
+{
+  uint16x4_t out_uint16x4_t;
+  uint32x4_t arg0_uint32x4_t;
+
+  out_uint16x4_t = vrshrn_n_u32 (arg0_uint32x4_t, 1);
+}
+
+/* { dg-final { scan-assembler "vrshrn\.i32\[ 	\]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */

gcc/testsuite/gcc.target/arm/neon/vRshrn_nu64.c

+/* Test the `vRshrn_nu64' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vRshrn_nu64 (void)
+{
+  uint32x2_t out_uint32x2_t;
+  uint64x2_t arg0_uint64x2_t;
+
+  out_uint32x2_t = vrshrn_n_u64 (arg0_uint64x2_t, 1);
+}
+
+/* { dg-final { scan-assembler "vrshrn\.i64\[ 	\]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */

gcc/testsuite/gcc.target/arm/neon/vRsraQ_ns16.c

+/* Test the `vRsraQ_ns16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vRsraQ_ns16 (void)
+{
+  int16x8_t out_int16x8_t;
+  int16x8_t arg0_int16x8_t;
+  int16x8_t arg1_int16x8_t;
+
+  out_int16x8_t = vrsraq_n_s16 (arg0_int16x8_t, arg1_int16x8_t, 1);
+}
+
+/* { dg-final { scan-assembler "vrsra\.s16\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */

gcc/testsuite/gcc.target/arm/neon/vRsraQ_ns32.c

+/* Test the `vRsraQ_ns32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vRsraQ_ns32 (void)
+{
+  int32x4_t out_int32x4_t;
+  int32x4_t arg0_int32x4_t;
+  int32x4_t arg1_int32x4_t;
+
+  out_int32x4_t = vrsraq_n_s32 (arg0_int32x4_t, arg1_int32x4_t, 1);
+}
+
+/* { dg-final { scan-assembler "vrsra\.s32\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */

gcc/testsuite/gcc.target/arm/neon/vRsraQ_ns64.c

+/* Test the `vRsraQ_ns64' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vRsraQ_ns64 (void)
+{
+  int64x2_t out_int64x2_t;
+  int64x2_t arg0_int64x2_t;
+  int64x2_t arg1_int64x2_t;
+
+  out_int64x2_t = vrsraq_n_s64 (arg0_int64x2_t, arg1_int64x2_t, 1);
+}
+
+/* { dg-final { scan-assembler "vrsra\.s64\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */

gcc/testsuite/gcc.target/arm/neon/vRsraQ_ns8.c

+/* Test the `vRsraQ_ns8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vRsraQ_ns8 (void)
+{
+  int8x16_t out_int8x16_t;
+  int8x16_t arg0_int8x16_t;
+  int8x16_t arg1_int8x16_t;
+
+  out_int8x16_t = vrsraq_n_s8 (arg0_int8x16_t, arg1_int8x16_t, 1);
+}
+
+/* { dg-final { scan-assembler "vrsra\.s8\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */

gcc/testsuite/gcc.target/arm/neon/vRsraQ_nu16.c

+/* Test the `vRsraQ_nu16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vRsraQ_nu16 (void)
+{
+  uint16x8_t out_uint16x8_t;
+  uint16x8_t arg0_uint16x8_t;
+  uint16x8_t arg1_uint16x8_t;
+
+  out_uint16x8_t = vrsraq_n_u16 (arg0_uint16x8_t, arg1_uint16x8_t, 1);
+}
+
+/* { dg-final { scan-assembler "vrsra\.u16\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */

gcc/testsuite/gcc.target/arm/neon/vRsraQ_nu32.c

+/* Test the `vRsraQ_nu32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vRsraQ_nu32 (void)
+{
+  uint32x4_t out_uint32x4_t;
+  uint32x4_t arg0_uint32x4_t;
+  uint32x4_t arg1_uint32x4_t;
+
+  out_uint32x4_t = vrsraq_n_u32 (arg0_uint32x4_t, arg1_uint32x4_t, 1);
+}
+
+/* { dg-final { scan-assembler "vrsra\.u32\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */

gcc/testsuite/gcc.target/arm/neon/vRsraQ_nu64.c

+/* Test the `vRsraQ_nu64' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vRsraQ_nu64 (void)
+{
+  uint64x2_t out_uint64x2_t;
+  uint64x2_t arg0_uint64x2_t;
+  uint64x2_t arg1_uint64x2_t;
+
+  out_uint64x2_t = vrsraq_n_u64 (arg0_uint64x2_t, arg1_uint64x2_t, 1);
+}
+
+/* { dg-final { scan-assembler "vrsra\.u64\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */

gcc/testsuite/gcc.target/arm/neon/vRsraQ_nu8.c

+/* Test the `vRsraQ_nu8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vRsraQ_nu8 (void)
+{
+  uint8x16_t out_uint8x16_t;
+  uint8x16_t arg0_uint8x16_t;
+  uint8x16_t arg1_uint8x16_t;
+
+  out_uint8x16_t = vrsraq_n_u8 (arg0_uint8x16_t, arg1_uint8x16_t, 1);
+}
+
+/* { dg-final { scan-assembler "vrsra\.u8\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */

gcc/testsuite/gcc.target/arm/neon/vRsra_ns16.c

+/* Test the `vRsra_ns16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vRsra_ns16 (void)
+{
+  int16x4_t out_int16x4_t;
+  int16x4_t arg0_int16x4_t;
+  int16x4_t arg1_int16x4_t;
+
+  out_int16x4_t = vrsra_n_s16 (arg0_int16x4_t, arg1_int16x4_t, 1);
+}
+
+/* { dg-final { scan-assembler "vrsra\.s16\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */

gcc/testsuite/gcc.target/arm/neon/vRsra_ns32.c

+/* Test the `vRsra_ns32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vRsra_ns32 (void)
+{
+  int32x2_t out_int32x2_t;
+  int32x2_t arg0_int32x2_t;
+  int32x2_t arg1_int32x2_t;
+
+  out_int32x2_t = vrsra_n_s32 (arg0_int32x2_t, arg1_int32x2_t, 1);
+}
+
+/* { dg-final { scan-assembler "vrsra\.s32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */

gcc/testsuite/gcc.target/arm/neon/vRsra_ns64.c

+/* Test the `vRsra_ns64' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vRsra_ns64 (void)
+{
+  int64x1_t out_int64x1_t;
+  int64x1_t arg0_int64x1_t;
+  int64x1_t arg1_int64x1_t;
+
+  out_int64x1_t = vrsra_n_s64 (arg0_int64x1_t, arg1_int64x1_t, 1);
+}
+
+/* { dg-final { scan-assembler "vrsra\.s64\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */

gcc/testsuite/gcc.target/arm/neon/vRsra_ns8.c

+/* Test the `vRsra_ns8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vRsra_ns8 (void)
+{
+  int8x8_t out_int8x8_t;
+  int8x8_t arg0_int8x8_t;
+  int8x8_t arg1_int8x8_t;
+
+  out_int8x8_t = vrsra_n_s8 (arg0_int8x8_t, arg1_int8x8_t, 1);
+}
+
+/* { dg-final { scan-assembler "vrsra\.s8\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */

gcc/testsuite/gcc.target/arm/neon/vRsra_nu16.c

+/* Test the `vRsra_nu16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vRsra_nu16 (void)
+{
+  uint16x4_t out_uint16x4_t;
+  uint16x4_t arg0_uint16x4_t;
+  uint16x4_t arg1_uint16x4_t;
+
+  out_uint16x4_t = vrsra_n_u16 (arg0_uint16x4_t, arg1_uint16x4_t, 1);
+}
+
+/* { dg-final { scan-assembler "vrsra\.u16\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */

gcc/testsuite/gcc.target/arm/neon/vRsra_nu32.c

+/* Test the `vRsra_nu32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vRsra_nu32 (void)
+{
+  uint32x2_t out_uint32x2_t;
+  uint32x2_t arg0_uint32x2_t;
+  uint32x2_t arg1_uint32x2_t;
+
+  out_uint32x2_t = vrsra_n_u32 (arg0_uint32x2_t, arg1_uint32x2_t, 1);
+}
+
+/* { dg-final { scan-assembler "vrsra\.u32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */

gcc/testsuite/gcc.target/arm/neon/vRsra_nu64.c

+/* Test the `vRsra_nu64' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vRsra_nu64 (void)
+{
+  uint64x1_t out_uint64x1_t;
+  uint64x1_t arg0_uint64x1_t;
+  uint64x1_t arg1_uint64x1_t;
+
+  out_uint64x1_t = vrsra_n_u64 (arg0_uint64x1_t, arg1_uint64x1_t, 1);
+}
+
+/* { dg-final { scan-assembler "vrsra\.u64\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */

gcc/testsuite/gcc.target/arm/neon/vRsra_nu8.c

+/* Test the `vRsra_nu8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vRsra_nu8 (void)
+{
+  uint8x8_t out_uint8x8_t;
+  uint8x8_t arg0_uint8x8_t;
+  uint8x8_t arg1_uint8x8_t;
+
+  out_uint8x8_t = vrsra_n_u8 (arg0_uint8x8_t, arg1_uint8x8_t, 1);
+}
+
+/* { dg-final { scan-assembler "vrsra\.u8\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */

gcc/testsuite/gcc.target/arm/neon/vRsubhns16.c

+/* Test the `vRsubhns16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vRsubhns16 (void)
+{
+  int8x8_t out_int8x8_t;
+  int16x8_t arg0_int16x8_t;
+  int16x8_t arg1_int16x8_t;
+
+  out_int8x8_t = vrsubhn_s16 (arg0_int16x8_t, arg1_int16x8_t);
+}
+
+/* { dg-final { scan-assembler "vrsubhn\.i16\[ 	\]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */

gcc/testsuite/gcc.target/arm/neon/vRsubhns32.c

+/* Test the `vRsubhns32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vRsubhns32 (void)
+{
+  int16x4_t out_int16x4_t;
+  int32x4_t arg0_int32x4_t;
+  int32x4_t arg1_int32x4_t;
+
+  out_int16x4_t = vrsubhn_s32 (arg0_int32x4_t, arg1_int32x4_t);
+}
+
+/* { dg-final { scan-assembler "vrsubhn\.i32\[ 	\]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */

gcc/testsuite/gcc.target/arm/neon/vRsubhns64.c

+/* Test the `vRsubhns64' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vRsubhns64 (void)
+{
+  int32x2_t out_int32x2_t;
+  int64x2_t arg0_int64x2_t;
+  int64x2_t arg1_int64x2_t;
+
+  out_int32x2_t = vrsubhn_s64 (arg0_int64x2_t, arg1_int64x2_t);
+}
+
+/* { dg-final { scan-assembler "vrsubhn\.i64\[ 	\]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */

gcc/testsuite/gcc.target/arm/neon/vRsubhnu16.c

+/* Test the `vRsubhnu16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vRsubhnu16 (void)
+{
+  uint8x8_t out_uint8x8_t;
+  uint16x8_t arg0_uint16x8_t;
+  uint16x8_t arg1_uint16x8_t;
+
+  out_uint8x8_t = vrsubhn_u16 (arg0_uint16x8_t, arg1_uint16x8_t);
+}
+
+/* { dg-final { scan-assembler "vrsubhn\.i16\[ 	\]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */

gcc/testsuite/gcc.target/arm/neon/vRsubhnu32.c

+/* Test the `vRsubhnu32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vRsubhnu32 (void)
+{
+  uint16x4_t out_uint16x4_t;
+  uint32x4_t arg0_uint32x4_t;
+  uint32x4_t arg1_uint32x4_t;
+
+  out_uint16x4_t = vrsubhn_u32 (arg0_uint32x4_t, arg1_uint32x4_t);
+}
+
+/* { dg-final { scan-assembler "vrsubhn\.i32\[ 	\]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */

gcc/testsuite/gcc.target/arm/neon/vRsubhnu64.c

+/* Test the `vRsubhnu64' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vRsubhnu64 (void)
+{
+  uint32x2_t out_uint32x2_t;
+  uint64x2_t arg0_uint64x2_t;
+  uint64x2_t arg1_uint64x2_t;
+
+  out_uint32x2_t = vrsubhn_u64 (arg0_uint64x2_t, arg1_uint64x2_t);
+}
+
+/* { dg-final { scan-assembler "vrsubhn\.i64\[ 	\]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */

gcc/testsuite/gcc.target/arm/neon/vabaQs16.c

+/* Test the `vabaQs16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vabaQs16 (void)
+{
+  int16x8_t out_int16x8_t;
+  int16x8_t arg0_int16x8_t;
+  int16x8_t arg1_int16x8_t;
+  int16x8_t arg2_int16x8_t;
+
+  out_int16x8_t = vabaq_s16 (arg0_int16x8_t, arg1_int16x8_t, arg2_int16x8_t);
+}
+
+/* { dg-final { scan-assembler "vaba\.s16\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */

gcc/testsuite/gcc.target/arm/neon/vabaQs32.c

+/* Test the `vabaQs32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vabaQs32 (void)
+{
+  int32x4_t out_int32x4_t;
+  int32x4_t arg0_int32x4_t;
+  int32x4_t arg1_int32x4_t;
+  int32x4_t arg2_int32x4_t;
+
+  out_int32x4_t = vabaq_s32 (arg0_int32x4_t, arg1_int32x4_t, arg2_int32x4_t);
+}
+
+/* { dg-final { scan-assembler "vaba\.s32\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */

gcc/testsuite/gcc.target/arm/neon/vabaQs8.c

+/* Test the `vabaQs8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vabaQs8 (void)
+{
+  int8x16_t out_int8x16_t;
+  int8x16_t arg0_int8x16_t;
+  int8x16_t arg1_int8x16_t;
+  int8x16_t arg2_int8x16_t;
+
+  out_int8x16_t = vabaq_s8 (arg0_int8x16_t, arg1_int8x16_t, arg2_int8x16_t);
+}
+
+/* { dg-final { scan-assembler "vaba\.s8\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */

gcc/testsuite/gcc.target/arm/neon/vabaQu16.c

+/* Test the `vabaQu16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vabaQu16 (void)
+{
+  uint16x8_t out_uint16x8_t;
+  uint16x8_t arg0_uint16x8_t;
+  uint16x8_t arg1_uint16x8_t;
+  uint16x8_t arg2_uint16x8_t;
+
+  out_uint16x8_t = vabaq_u16 (arg0_uint16x8_t, arg1_uint16x8_t, arg2_uint16x8_t);
+}
+
+/* { dg-final { scan-assembler "vaba\.u16\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */

gcc/testsuite/gcc.target/arm/neon/vabaQu32.c

+/* Test the `vabaQu32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vabaQu32 (void)
+{
+  uint32x4_t out_uint32x4_t;
+  uint32x4_t arg0_uint32x4_t;
+  uint32x4_t arg1_uint32x4_t;
+  uint32x4_t arg2_uint32x4_t;
+
+  out_uint32x4_t = vabaq_u32 (arg0_uint32x4_t, arg1_uint32x4_t, arg2_uint32x4_t);
+}
+
+/* { dg-final { scan-assembler "vaba\.u32\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */

gcc/testsuite/gcc.target/arm/neon/vabaQu8.c

+/* Test the `vabaQu8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vabaQu8 (void)
+{
+  uint8x16_t out_uint8x16_t;
+  uint8x16_t arg0_uint8x16_t;
+  uint8x16_t arg1_uint8x16_t;
+  uint8x16_t arg2_uint8x16_t;
+
+  out_uint8x16_t = vabaq_u8 (arg0_uint8x16_t, arg1_uint8x16_t, arg2_uint8x16_t);
+}
+
+/* { dg-final { scan-assembler "vaba\.u8\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */

gcc/testsuite/gcc.target/arm/neon/vabals16.c

+/* Test the `vabals16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vabals16 (void)
+{
+  int32x4_t out_int32x4_t;
+  int32x4_t arg0_int32x4_t;
+  int16x4_t arg1_int16x4_t;
+  int16x4_t arg2_int16x4_t;
+
+  out_int32x4_t = vabal_s16 (arg0_int32x4_t, arg1_int16x4_t, arg2_int16x4_t);
+}
+
+/* { dg-final { scan-assembler "vabal\.s16\[ 	\]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */

gcc/testsuite/gcc.target/arm/neon/vabals32.c

+/* Test the `vabals32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vabals32 (void)
+{
+  int64x2_t out_int64x2_t;
+  int64x2_t arg0_int64x2_t;
+  int32x2_t arg1_int32x2_t;
+  int32x2_t arg2_int32x2_t;
+
+  out_int64x2_t = vabal_s32 (arg0_int64x2_t, arg1_int32x2_t, arg2_int32x2_t);
+}
+
+/* { dg-final { scan-assembler "vabal\.s32\[ 	\]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */

gcc/testsuite/gcc.target/arm/neon/vabals8.c

+/* Test the `vabals8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vabals8 (void)
+{
+  int16x8_t out_int16x8_t;
+  int16x8_t arg0_int16x8_t;
+  int8x8_t arg1_int8x8_t;
+  int8x8_t arg2_int8x8_t;
+
+  out_int16x8_t = vabal_s8 (arg0_int16x8_t, arg1_int8x8_t, arg2_int8x8_t);
+}
+
+/* { dg-final { scan-assembler "vabal\.s8\[ 	\]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */

gcc/testsuite/gcc.target/arm/neon/vabalu16.c

+/* Test the `vabalu16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vabalu16 (void)
+{
+  uint32x4_t out_uint32x4_t;
+  uint32x4_t arg0_uint32x4_t;
+  uint16x4_t arg1_uint16x4_t;
+  uint16x4_t arg2_uint16x4_t;
+
+  out_uint32x4_t = vabal_u16 (arg0_uint32x4_t, arg1_uint16x4_t, arg2_uint16x4_t);
+}
+
+/* { dg-final { scan-assembler "vabal\.u16\[ 	\]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */

gcc/testsuite/gcc.target/arm/neon/vabalu32.c

+/* Test the `vabalu32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vabalu32 (void)
+{
+  uint64x2_t out_uint64x2_t;
+  uint64x2_t arg0_uint64x2_t;
+  uint32x2_t arg1_uint32x2_t;
+  uint32x2_t arg2_uint32x2_t;
+
+  out_uint64x2_t = vabal_u32 (arg0_uint64x2_t, arg1_uint32x2_t, arg2_uint32x2_t);
+}
+
+/* { dg-final { scan-assembler "vabal\.u32\[ 	\]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */

gcc/testsuite/gcc.target/arm/neon/vabalu8.c

+/* Test the `vabalu8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vabalu8 (void)
+{
+  uint16x8_t out_uint16x8_t;
+  uint16x8_t arg0_uint16x8_t;
+  uint8x8_t arg1_uint8x8_t;
+  uint8x8_t arg2_uint8x8_t;
+
+  out_uint16x8_t = vabal_u8 (arg0_uint16x8_t, arg1_uint8x8_t, arg2_uint8x8_t);
+}
+
+/* { dg-final { scan-assembler "vabal\.u8\[ 	\]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */

gcc/testsuite/gcc.target/arm/neon/vabas16.c

+/* Test the `vabas16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vabas16 (void)
+{
+  int16x4_t out_int16x4_t;
+  int16x4_t arg0_int16x4_t;
+  int16x4_t arg1_int16x4_t;
+  int16x4_t arg2_int16x4_t;
+
+  out_int16x4_t = vaba_s16 (arg0_int16x4_t, arg1_int16x4_t, arg2_int16x4_t);
+}
+
+/* { dg-final { scan-assembler "vaba\.s16\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */

gcc/testsuite/gcc.target/arm/neon/vabas32.c

+/* Test the `vabas32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vabas32 (void)
+{
+  int32x2_t out_int32x2_t;
+  int32x2_t arg0_int32x2_t;
+  int32x2_t arg1_int32x2_t;
+  int32x2_t arg2_int32x2_t;
+
+  out_int32x2_t = vaba_s32 (arg0_int32x2_t, arg1_int32x2_t, arg2_int32x2_t);
+}
+
+/* { dg-final { scan-assembler "vaba\.s32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */

gcc/testsuite/gcc.target/arm/neon/vabas8.c

+/* Test the `vabas8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vabas8 (void)
+{
+  int8x8_t out_int8x8_t;
+  int8x8_t arg0_int8x8_t;
+  int8x8_t arg1_int8x8_t;
+  int8x8_t arg2_int8x8_t;
+
+  out_int8x8_t = vaba_s8 (arg0_int8x8_t, arg1_int8x8_t, arg2_int8x8_t);
+}
+
+/* { dg-final { scan-assembler "vaba\.s8\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */

gcc/testsuite/gcc.target/arm/neon/vabau16.c

+/* Test the `vabau16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vabau16 (void)
+{
+  uint16x4_t out_uint16x4_t;
+  uint16x4_t arg0_uint16x4_t;
+  uint16x4_t arg1_uint16x4_t;
+  uint16x4_t arg2_uint16x4_t;
+
+  out_uint16x4_t = vaba_u16 (arg0_uint16x4_t, arg1_uint16x4_t, arg2_uint16x4_t);
+}
+
+/* { dg-final { scan-assembler "vaba\.u16\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */

gcc/testsuite/gcc.target/arm/neon/vabau32.c

+/* Test the `vabau32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vabau32 (void)
+{
+  uint32x2_t out_uint32x2_t;
+  uint32x2_t arg0_uint32x2_t;
+  uint32x2_t arg1_uint32x2_t;
+  uint32x2_t arg2_uint32x2_t;
+
+  out_uint32x2_t = vaba_u32 (arg0_uint32x2_t, arg1_uint32x2_t, arg2_uint32x2_t);
+}
+
+/* { dg-final { scan-assembler "vaba\.u32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */

gcc/testsuite/gcc.target/arm/neon/vabau8.c

+/* Test the `vabau8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vabau8 (void)
+{
+  uint8x8_t out_uint8x8_t;
+  uint8x8_t arg0_uint8x8_t;
+  uint8x8_t arg1_uint8x8_t;
+  uint8x8_t arg2_uint8x8_t;
+
+  out_uint8x8_t = vaba_u8 (arg0_uint8x8_t, arg1_uint8x8_t, arg2_uint8x8_t);
+}
+
+/* { dg-final { scan-assembler "vaba\.u8\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */

gcc/testsuite/gcc.target/arm/neon/vabdQf32.c

+/* Test the `vabdQf32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vabdQf32 (void)
+{
+  float32x4_t out_float32x4_t;
+  float32x4_t arg0_float32x4_t;
+  float32x4_t arg1_float32x4_t;
+
+  out_float32x4_t = vabdq_f32 (arg0_float32x4_t, arg1_float32x4_t);
+}
+
+/* { dg-final { scan-assembler "vabd\.f32\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */