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Commit 8ef4f42c by Uros Bizjak Committed by Uros Bizjak
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i386.md (*fpatanxf3_i387, [...]): New insn patterns. 

	* config/i386/i386.md (*fpatanxf3_i387, fpatan_extend<mode>xf3_i387):
	New insn patterns.
	(atan2sf3_1, atan2df3_1, atan2xf3_1): Remove insn patterns.
	(atan2xf3): Directly generate RTL pattern.
	(atan2<mode>3): Rename from atan2sf3 and atan2df3 and macroize insn
	patterns using X87MODEF12 mode macro.  Use fpatan_extend<mode>xf3_i387
	and truncate result to requested mode.  Use SSE_FLOAT_MODE_P to
	disable patterns for SSE math.
	(atan<mode>2): Rename from atansf2 and atandf2 and macroize insn
	patterns using X87MODEF12 mode macro.  Use fpatan_extend<mode>xf3_i387
	and truncate result to requested mode.  Use SSE_FLOAT_MODE_P to
	disable patterns for SSE math.

From-SVN: r120950
parent 15e92535
Showing with 68 additions and 88 deletions
gcc/ChangeLog
2007-01-19 Uros Bizjak <ubizjak@gmail.com>
* config/i386/i386.md (*fpatanxf3_i387, fpatan_extend<mode>xf3_i387):
New insn patterns.
(atan2sf3_1, atan2df3_1, atan2xf3_1): Remove insn patterns.
(atan2xf3): Directly generate RTL pattern.
(atan2<mode>3): Rename from atan2sf3 and atan2df3 and macroize insn
patterns using X87MODEF12 mode macro. Use fpatan_extend<mode>xf3_i387
and truncate result to requested mode. Use SSE_FLOAT_MODE_P to
disable patterns for SSE math.
(atan<mode>2): Rename from atansf2 and atandf2 and macroize insn
patterns using X87MODEF12 mode macro. Use fpatan_extend<mode>xf3_i387
and truncate result to requested mode. Use SSE_FLOAT_MODE_P to
disable patterns for SSE math.
2007-01-19 Alexandre Oliva <aoliva@redhat.com>
* libgcc-std.ver: Fix typo in %inherit for GCC_4.3.0.
......
gcc/config/i386/i386.md
......@@ -15927,110 +15927,57 @@
DONE;
})
(define_insn "atan2df3_1"
[(set (match_operand:DF 0 "register_operand" "=f")
(unspec:DF [(match_operand:DF 2 "register_operand" "0")
(match_operand:DF 1 "register_operand" "u")]
UNSPEC_FPATAN))
(clobber (match_scratch:DF 3 "=1"))]
"TARGET_USE_FANCY_MATH_387
&& (!(TARGET_SSE2 && TARGET_SSE_MATH) || TARGET_MIX_SSE_I387)
&& flag_unsafe_math_optimizations"
"fpatan"
[(set_attr "type" "fpspc")
(set_attr "mode" "DF")])
(define_expand "atan2df3"
[(use (match_operand:DF 0 "register_operand" ""))
(use (match_operand:DF 2 "register_operand" ""))
(use (match_operand:DF 1 "register_operand" ""))]
"TARGET_USE_FANCY_MATH_387
&& (!(TARGET_SSE2 && TARGET_SSE_MATH) || TARGET_MIX_SSE_I387)
&& flag_unsafe_math_optimizations"
{
rtx copy = gen_reg_rtx (DFmode);
emit_move_insn (copy, operands[1]);
emit_insn (gen_atan2df3_1 (operands[0], copy, operands[2]));
DONE;
})
(define_expand "atandf2"
[(parallel [(set (match_operand:DF 0 "register_operand" "")
(unspec:DF [(match_dup 2)
(match_operand:DF 1 "register_operand" "")]
UNSPEC_FPATAN))
(clobber (match_scratch:DF 3 ""))])]
"TARGET_USE_FANCY_MATH_387
&& (!(TARGET_SSE2 && TARGET_SSE_MATH) || TARGET_MIX_SSE_I387)
&& flag_unsafe_math_optimizations"
{
operands[2] = gen_reg_rtx (DFmode);
emit_move_insn (operands[2], CONST1_RTX (DFmode)); /* fld1 */
})
(define_insn "atan2sf3_1"
[(set (match_operand:SF 0 "register_operand" "=f")
(unspec:SF [(match_operand:SF 2 "register_operand" "0")
(match_operand:SF 1 "register_operand" "u")]
UNSPEC_FPATAN))
(clobber (match_scratch:SF 3 "=1"))]
(define_insn "*fpatanxf3_i387"
[(set (match_operand:XF 0 "register_operand" "=f")
(unspec:XF [(match_operand:XF 1 "register_operand" "0")
(match_operand:XF 2 "register_operand" "u")]
UNSPEC_FPATAN))
(clobber (match_scratch:XF 3 "=2"))]
"TARGET_USE_FANCY_MATH_387
&& (!TARGET_SSE_MATH || TARGET_MIX_SSE_I387)
&& flag_unsafe_math_optimizations"
"fpatan"
[(set_attr "type" "fpspc")
(set_attr "mode" "SF")])
(define_expand "atan2sf3"
[(use (match_operand:SF 0 "register_operand" ""))
(use (match_operand:SF 2 "register_operand" ""))
(use (match_operand:SF 1 "register_operand" ""))]
"TARGET_USE_FANCY_MATH_387
&& (!TARGET_SSE_MATH || TARGET_MIX_SSE_I387)
&& flag_unsafe_math_optimizations"
{
rtx copy = gen_reg_rtx (SFmode);
emit_move_insn (copy, operands[1]);
emit_insn (gen_atan2sf3_1 (operands[0], copy, operands[2]));
DONE;
})
(define_expand "atansf2"
[(parallel [(set (match_operand:SF 0 "register_operand" "")
(unspec:SF [(match_dup 2)
(match_operand:SF 1 "register_operand" "")]
UNSPEC_FPATAN))
(clobber (match_scratch:SF 3 ""))])]
"TARGET_USE_FANCY_MATH_387
&& (!TARGET_SSE_MATH || TARGET_MIX_SSE_I387)
&& flag_unsafe_math_optimizations"
{
operands[2] = gen_reg_rtx (SFmode);
emit_move_insn (operands[2], CONST1_RTX (SFmode)); /* fld1 */
})
(set_attr "mode" "XF")])
(define_insn "atan2xf3_1"
(define_insn "fpatan_extend<mode>xf3_i387"
[(set (match_operand:XF 0 "register_operand" "=f")
(unspec:XF [(match_operand:XF 2 "register_operand" "0")
(match_operand:XF 1 "register_operand" "u")]
(unspec:XF [(float_extend:XF
(match_operand:X87MODEF12 1 "register_operand" "0"))
(float_extend:XF
(match_operand:X87MODEF12 2 "register_operand" "u"))]
UNSPEC_FPATAN))
(clobber (match_scratch:XF 3 "=1"))]
(clobber (match_scratch:XF 3 "=2"))]
"TARGET_USE_FANCY_MATH_387
&& (!(SSE_FLOAT_MODE_P (<MODE>mode) && TARGET_SSE_MATH)
|| TARGET_MIX_SSE_I387)
&& flag_unsafe_math_optimizations"
"fpatan"
[(set_attr "type" "fpspc")
(set_attr "mode" "XF")])
(define_expand "atan2xf3"
[(use (match_operand:XF 0 "register_operand" ""))
(use (match_operand:XF 2 "register_operand" ""))
(use (match_operand:XF 1 "register_operand" ""))]
[(parallel [(set (match_operand:XF 0 "register_operand" "")
(unspec:XF [(match_operand:XF 2 "register_operand" "")
(match_operand:XF 1 "register_operand" "")]
UNSPEC_FPATAN))
(clobber (match_scratch:XF 3 ""))])]
"TARGET_USE_FANCY_MATH_387
&& flag_unsafe_math_optimizations"
"")
(define_expand "atan2<mode>3"
[(use (match_operand:X87MODEF12 0 "register_operand" ""))
(use (match_operand:X87MODEF12 1 "register_operand" ""))
(use (match_operand:X87MODEF12 2 "register_operand" ""))]
"TARGET_USE_FANCY_MATH_387
&& (!(SSE_FLOAT_MODE_P (<MODE>mode) && TARGET_SSE_MATH)
|| TARGET_MIX_SSE_I387)
&& flag_unsafe_math_optimizations"
{
rtx copy = gen_reg_rtx (XFmode);
emit_move_insn (copy, operands[1]);
emit_insn (gen_atan2xf3_1 (operands[0], copy, operands[2]));
rtx op0 = gen_reg_rtx (XFmode);
emit_insn (gen_fpatan_extend<mode>xf3_i387 (op0, operands[2], operands[1]));
emit_insn (gen_truncxf<mode>2_i387_noop (operands[0], op0));
DONE;
})
......@@ -16038,7 +15985,7 @@
[(parallel [(set (match_operand:XF 0 "register_operand" "")
(unspec:XF [(match_dup 2)
(match_operand:XF 1 "register_operand" "")]
UNSPEC_FPATAN))
UNSPEC_FPATAN))
(clobber (match_scratch:XF 3 ""))])]
"TARGET_USE_FANCY_MATH_387
&& flag_unsafe_math_optimizations"
......@@ -16047,6 +15994,24 @@
emit_move_insn (operands[2], CONST1_RTX (XFmode)); /* fld1 */
})
(define_expand "atan<mode>2"
[(use (match_operand:X87MODEF12 0 "register_operand" ""))
(use (match_operand:X87MODEF12 1 "register_operand" ""))]
"TARGET_USE_FANCY_MATH_387
&& (!(SSE_FLOAT_MODE_P (<MODE>mode) && TARGET_SSE_MATH)
|| TARGET_MIX_SSE_I387)
&& flag_unsafe_math_optimizations"
{
rtx op0 = gen_reg_rtx (XFmode);
operands[2] = gen_reg_rtx (<MODE>mode);
emit_move_insn (operands[2], CONST1_RTX (<MODE>mode)); /* fld1 */
emit_insn (gen_fpatan_extend<mode>xf3_i387 (op0, operands[2], operands[1]));
emit_insn (gen_truncxf<mode>2_i387_noop (operands[0], op0));
DONE;
})
(define_expand "asindf2"
[(set (match_dup 2)
(float_extend:XF (match_operand:DF 1 "register_operand" "")))
......
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