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riscv-gcc-1
Commit 8ed43adf by Kazu Hirata Committed by Kazu Hirata
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h8300.md: Replace dead bit extraction patterns with ones that work. 

	* config/h8300/h8300.md: Replace dead bit extraction patterns
	with ones that work.

From-SVN: r49269
parent 917afb0c
Showing with 32 additions and 104 deletions
gcc/ChangeLog
2002-01-27 Kazu Hirata <kazu@hxi.com>
* config/h8300/h8300.md: Replace dead bit extraction patterns
with ones that work.
Sun Jan 27 13:23:40 2002 Richard Kenner <kenner@vlsi1.ultra.nyu.edu>
* emit-rtl.c (get_mem_attrs): Don't default alignment for non-BLKmode
......
gcc/config/h8300/h8300.md
......@@ -2010,135 +2010,58 @@
;;
;; Normal loads with a 32bit destination.
;;
;; Yes, all three cases are needed.
;;
(define_insn ""
[(set (match_operand:SI 0 "register_operand" "=&r")
(zero_extract:SI (match_operand:HI 1 "register_operand" "r")
(const_int 1)
(match_operand:HI 2 "const_int_operand" "n")))]
""
"* return output_simode_bld (0, 0, operands);"
[(set_attr "cc" "clobber")
(set (attr "length")
(if_then_else (eq (symbol_ref "TARGET_H8300H || TARGET_H8300S")
(const_int 0))
(const_int 10)
(const_int 8)))])
(define_insn ""
[(set (match_operand:SI 0 "register_operand" "=&r")
(and:SI (zero_extend:SI
(lshiftrt:QI
(match_operand:QI 1 "bit_operand" "Ur")
(match_operand:QI 2 "const_int_operand" "n")))
(const_int 1)))]
""
(match_operand 2 "const_int_operand" "n")))]
"TARGET_H8300
&& INTVAL (operands[2]) < 16"
"* return output_simode_bld (0, 0, operands);"
[(set_attr "cc" "clobber")
(set (attr "length")
(if_then_else (eq (symbol_ref "TARGET_H8300H || TARGET_H8300S")
(const_int 0))
(const_int 10)
(const_int 8)))])
(set_attr "length" "6")])
(define_insn ""
[(set (match_operand:SI 0 "register_operand" "=&r")
(and:SI (zero_extend:SI
(lshiftrt:HI
(match_operand:HI 1 "bit_operand" "Ur")
(match_operand:HI 2 "const_int_operand" "n")))
(const_int 1)))]
""
(zero_extract:SI (match_operand:SI 1 "register_operand" "r")
(const_int 1)
(match_operand 2 "const_int_operand" "n")))]
"(TARGET_H8300H || TARGET_H8300S)
&& INTVAL (operands[2]) < 16"
"* return output_simode_bld (0, 0, operands);"
[(set_attr "cc" "clobber")
(set (attr "length")
(if_then_else (eq (symbol_ref "TARGET_H8300H || TARGET_H8300S")
(const_int 0))
(const_int 10)
(const_int 8)))])
(set_attr "length" "6")])
;;
;; Inverted loads with a 32bit destination.
;;
;; Yes, all five cases are needed.
;;
(define_insn ""
[(set (match_operand:SI 0 "register_operand" "=&r")
(and:SI (not:SI
(zero_extend:SI
(lshiftrt:HI (match_operand:HI 1 "bit_operand" "Ur")
(match_operand:HI 2 "const_int_operand" "n"))))
(const_int 1)))]
""
"* return output_simode_bld (1, 0, operands);"
[(set_attr "cc" "clobber")
(set (attr "length")
(if_then_else (eq (symbol_ref "TARGET_H8300H || TARGET_H8300S")
(const_int 0))
(const_int 10)
(const_int 8)))])
(define_insn ""
[(set (match_operand:SI 0 "register_operand" "=&r")
(and:SI (not:SI
(zero_extend:SI
(lshiftrt:QI (match_operand:QI 1 "bit_operand" "Ur")
(match_operand:QI 2 "const_int_operand" "n"))))
(const_int 1)))]
""
"* return output_simode_bld (1, 0, operands);"
[(set_attr "cc" "clobber")
(set (attr "length")
(if_then_else (eq (symbol_ref "TARGET_H8300H || TARGET_H8300S")
(const_int 0))
(const_int 10)
(const_int 8)))])
(define_insn ""
[(set (match_operand:SI 0 "register_operand" "=&r")
(and:SI (not:SI
(subreg:SI
(lshiftrt:HI
(match_operand:HI 1 "bit_operand" "Ur")
(match_operand:HI 2 "const_int_operand" "n")) 0))
(const_int 1)))]
"1"
"* return output_simode_bld (1, 0, operands);"
[(set_attr "cc" "clobber")
(set (attr "length")
(if_then_else (eq (symbol_ref "TARGET_H8300H || TARGET_H8300S")
(const_int 0))
(const_int 10)
(const_int 8)))])
(define_insn ""
[(set (match_operand:SI 0 "register_operand" "=&r")
(and:SI (not:SI
(subreg:SI
(lshiftrt:QI
(match_operand:QI 1 "bit_operand" "Ur")
(match_operand:QI 2 "const_int_operand" "n")) 0))
(const_int 1)))]
"1"
(zero_extract:SI (xor:HI (match_operand:HI 1 "register_operand" "r")
(match_operand:HI 3 "const_int_operand" "n"))
(const_int 1)
(match_operand 2 "const_int_operand" "n")))]
"TARGET_H8300
&& INTVAL (operands[2]) < 16
&& (1 << INTVAL (operands[2])) == INTVAL (operands[3])"
"* return output_simode_bld (1, 0, operands);"
[(set_attr "cc" "clobber")
(set (attr "length")
(if_then_else (eq (symbol_ref "TARGET_H8300H || TARGET_H8300S")
(const_int 0))
(const_int 10)
(const_int 8)))])
(set_attr "length" "6")])
(define_insn ""
[(set (match_operand:SI 0 "register_operand" "=&r")
(zero_extract:SI (xor:HI (match_operand:HI 1 "register_operand" "r")
(match_operand:HI 3 "p_operand" "P"))
(zero_extract:SI (xor:SI (match_operand:SI 1 "register_operand" "r")
(match_operand 3 "const_int_operand" "n"))
(const_int 1)
(match_operand:HI 2 "const_int_operand" "n")))]
"(1 << INTVAL (operands[2])) == INTVAL (operands[3])"
"sub.w %0,%0\;bild %Z2,%Y1\;bst #0,%X0"
(match_operand 2 "const_int_operand" "n")))]
"(TARGET_H8300H || TARGET_H8300S)
&& INTVAL (operands[2]) < 16
&& (1 << INTVAL (operands[2])) == INTVAL (operands[3])"
"* return output_simode_bld (1, 0, operands);"
[(set_attr "cc" "clobber")
(set_attr "length" "8")])
(set_attr "length" "6")])
(define_expand "insv"
[(set (zero_extract:HI (match_operand:HI 0 "general_operand" "")
......
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