re PR rtl-optimization/39453 (ICE : in init_seqno, at sel-sched.c:6433)

2010-01-14  Alexander Monakov  <amonakov@ispras.ru>

	PR rtl-optimization/39453
	PR rtl-optimization/42246
	* sel-sched-ir.c (considered_for_pipelining_p): Do not test
	for pipelining_p.
	(sel_add_loop_preheaders): Add preheader to last_added_blocks.

	* gcc.dg/pr39453.c: New.
	* gcc.dg/pr42246.c: New.

From-SVN: r155892

gcc/ChangeLog

+2010-01-14  Alexander Monakov  <amonakov@ispras.ru>
+
+	PR rtl-optimization/39453
+	PR rtl-optimization/42246
+	* sel-sched-ir.c (considered_for_pipelining_p): Do not test
+	for pipelining_p.
+	(sel_add_loop_preheaders): Add preheader to last_added_blocks.
+
 2010-01-14  Andrey Belevantsev  <abel@ispras.ru>
 	    Alexander Monakov  <amonakov@ispras.ru>
 

gcc/sel-sched-ir.c

@@ -5883,7 +5883,7 @@ considered_for_pipelining_p (struct loop *loop)
      latch.  We can't use header here, because this header could be
      just removed preheader and it will give us the wrong region number.
      Latch can't be used because it could be in the inner loop too.  */
-  if (LOOP_MARKED_FOR_PIPELINING_P (loop) && pipelining_p)
+  if (LOOP_MARKED_FOR_PIPELINING_P (loop))
     {
       int rgn = CONTAINING_RGN (loop->latch->index);
 
@@ -6032,7 +6032,10 @@ sel_add_loop_preheaders (void)
   for (i = 0;
        VEC_iterate (basic_block, preheader_blocks, i, bb);
        i++)
+    {
+      VEC_safe_push (basic_block, heap, last_added_blocks, bb);
       sel_add_bb (bb);
+    }
 
   VEC_free (basic_block, heap, preheader_blocks);
 }

gcc/testsuite/ChangeLog

 2010-01-14  Alexander Monakov <amonakov@ispras.ru>
 
+	PR rtl-optimization/39453
+	PR rtl-optimization/42246
+	* gcc.dg/pr39453.c: New.
+	* gcc.dg/pr42246.c: New.
+
+2010-01-14  Alexander Monakov <amonakov@ispras.ru>
+
 	PR middle-end/42245
 	* gcc.dg/pr42245.c: New.
 	* gcc.dg/pr42245-2.c: New.

gcc/testsuite/gcc.dg/pr39453.c

+/* { dg-do compile { target powerpc*-*-* ia64-*-* x86_64-*-* } } */
+/* { dg-options "-O2 -fselective-scheduling2 -fsel-sched-pipelining -fsel-sched-pipelining-outer-loops" } */
+
+int foo(int k, int n)
+{
+  int i;
+  for (i = 0; i < n; i += 8) {
+    int j;
+    for (j = 0; j < n; j += 8) {
+      while (k < n) {
+        k += 8;
+      }
+    }
+  }
+  return k;
+}
+
+

gcc/testsuite/gcc.dg/pr42246.c

+/* { dg-do compile { target powerpc*-*-* ia64-*-* x86_64-*-* } } */
+/* { dg-options "-O2 -fselective-scheduling -fsel-sched-pipelining -fsel-sched-pipelining-outer-loops" } */
+
+typedef enum
+{
+  empty = 0, pawn = 1, knight = 2, king = 3, bishop = 5, rook = 6, queen = 7
+}
+PIECE;
+extern int p_values[15];
+extern int *last[65];
+int
+Quiesce (int alpha, int beta, int wtm, int ply)
+{
+  register int initial_alpha, value, delta;
+  register int *goodmv, *movep, moves = 0, *sortv, temp;
+  for (movep = last[ply - 1]; movep < last[ply]; movep++)
+    if (p_values[(((*movep) >> 15) & 7) + 7] +
+        p_values[(((*movep) >> 18) & 7) + 7] >= delta)
+      {
+        register int done;
+        register int *end = last[ply - 1] + moves - 1;
+        do
+          {
+            done = 1;
+            movep = last[ply - 1];
+            for (; movep < end; movep++, sortv++)
+              if (*sortv < *(sortv + 1))
+                {
+                  *(movep + 1) = temp;
+                  done = 0;
+                }
+          }
+        while (!done);
+      }
+}
+