re PR target/80846 (auto-vectorized AVX2 horizontal sum should narrow to 128b…

re PR target/80846 (auto-vectorized AVX2 horizontal sum should narrow to 128b right away, to be more efficient for Ryzen and Intel)

	PR target/80846
	* config/rs6000/vsx.md (vextract_fp_from_shorth,
	vextract_fp_from_shortl): Add element mode after mode in gen_vec_init*
	calls.

From-SVN: r250784

gcc/ChangeLog

+2017-08-01  Jakub Jelinek  <jakub@redhat.com>
+
+	PR target/80846
+	* config/rs6000/vsx.md (vextract_fp_from_shorth,
+	vextract_fp_from_shortl): Add element mode after mode in gen_vec_init*
+	calls.
+
 2017-08-01  Jerome Lambourg  <lambourg@adacore.com>
             Doug Rupp  <rupp@adacore.com>
             Olivier Hainque  <hainque@adacore.com>

gcc/config/rs6000/vsx.md

@@ -4523,7 +4523,7 @@
      inputs in half words 1,3,5,7 (IBM numbering).  Use xxperm to move
      src half words 0,1,2,3 for the conversion instruction.  */
   v = gen_rtvec_v (16, rvals);
-  emit_insn (gen_vec_initv16qi (mask, gen_rtx_PARALLEL (V16QImode, v)));
+  emit_insn (gen_vec_initv16qiqi (mask, gen_rtx_PARALLEL (V16QImode, v)));
   emit_insn (gen_altivec_vperm_v8hiv16qi (tmp, operands[1],
 					  operands[1], mask));
   emit_insn (gen_vsx_xvcvhpsp (operands[0], tmp));
@@ -4552,7 +4552,7 @@
      inputs in half words 1,3,5,7 (IBM numbering).  Use xxperm to move
      src half words 4,5,6,7 for the conversion instruction.  */
   v = gen_rtvec_v (16, rvals);
-  emit_insn (gen_vec_initv16qi (mask, gen_rtx_PARALLEL (V16QImode, v)));
+  emit_insn (gen_vec_initv16qiqi (mask, gen_rtx_PARALLEL (V16QImode, v)));
   emit_insn (gen_altivec_vperm_v8hiv16qi (tmp, operands[1],
 					  operands[1], mask));
   emit_insn (gen_vsx_xvcvhpsp (operands[0], tmp));