Commit 8d8563ae by David S. Miller

sparc.md (shift insns): Do not mask off second operand...

2002-05-06  David S. Miller  <davem@redhat.com>

	* config/sparc/sparc.md (shift insns): Do not mask off
	second operand, 'I' constraint and SHIFT_COUNT_TRUNCATED
	take care of it.

From-SVN: r53238
parent 97320a3f
...@@ -7241,10 +7241,6 @@ ...@@ -7241,10 +7241,6 @@
"" ""
"* "*
{ {
if (GET_CODE (operands[2]) == CONST_INT
&& (unsigned HOST_WIDE_INT) INTVAL (operands[2]) > 31)
operands[2] = GEN_INT (INTVAL (operands[2]) & 0x1f);
if (operands[2] == const1_rtx) if (operands[2] == const1_rtx)
return \"add\\t%1, %1, %0\"; return \"add\\t%1, %1, %0\";
return \"sll\\t%1, %2, %0\"; return \"sll\\t%1, %2, %0\";
...@@ -7276,10 +7272,6 @@ ...@@ -7276,10 +7272,6 @@
"TARGET_ARCH64" "TARGET_ARCH64"
"* "*
{ {
if (GET_CODE (operands[2]) == CONST_INT
&& (unsigned HOST_WIDE_INT) INTVAL (operands[2]) > 63)
operands[2] = GEN_INT (INTVAL (operands[2]) & 0x3f);
if (operands[2] == const1_rtx) if (operands[2] == const1_rtx)
return \"add\\t%1, %1, %0\"; return \"add\\t%1, %1, %0\";
return \"sllx\\t%1, %2, %0\"; return \"sllx\\t%1, %2, %0\";
...@@ -7344,10 +7336,6 @@ ...@@ -7344,10 +7336,6 @@
"" ""
"* "*
{ {
if (GET_CODE (operands[2]) == CONST_INT
&& (unsigned HOST_WIDE_INT) INTVAL (operands[2]) > 31)
operands[2] = GEN_INT (INTVAL (operands[2]) & 0x1f);
return \"sra\\t%1, %2, %0\"; return \"sra\\t%1, %2, %0\";
}" }"
[(set_attr "type" "shift")]) [(set_attr "type" "shift")])
...@@ -7405,10 +7393,6 @@ ...@@ -7405,10 +7393,6 @@
"TARGET_ARCH64" "TARGET_ARCH64"
"* "*
{ {
if (GET_CODE (operands[2]) == CONST_INT
&& (unsigned HOST_WIDE_INT) INTVAL (operands[2]) > 63)
operands[2] = GEN_INT (INTVAL (operands[2]) & 0x3f);
return \"srax\\t%1, %2, %0\"; return \"srax\\t%1, %2, %0\";
}" }"
[(set_attr "type" "shift")]) [(set_attr "type" "shift")])
...@@ -7431,10 +7415,6 @@ ...@@ -7431,10 +7415,6 @@
"" ""
"* "*
{ {
if (GET_CODE (operands[2]) == CONST_INT
&& (unsigned HOST_WIDE_INT) INTVAL (operands[2]) > 31)
operands[2] = GEN_INT (INTVAL (operands[2]) & 0x1f);
return \"srl\\t%1, %2, %0\"; return \"srl\\t%1, %2, %0\";
}" }"
[(set_attr "type" "shift")]) [(set_attr "type" "shift")])
...@@ -7502,10 +7482,6 @@ ...@@ -7502,10 +7482,6 @@
"TARGET_ARCH64" "TARGET_ARCH64"
"* "*
{ {
if (GET_CODE (operands[2]) == CONST_INT
&& (unsigned HOST_WIDE_INT) INTVAL (operands[2]) > 63)
operands[2] = GEN_INT (INTVAL (operands[2]) & 0x3f);
return \"srlx\\t%1, %2, %0\"; return \"srlx\\t%1, %2, %0\";
}" }"
[(set_attr "type" "shift")]) [(set_attr "type" "shift")])
......
Markdown is supported
0% or
You are about to add 0 people to the discussion. Proceed with caution.
Finish editing this message first!
Please register or to comment