Skip to content

R
riscv-gcc-1
Commit 8d75ab4d by H.J. Lu Committed by H.J. Lu
Options

i386: Fix a typo in comments for for "Yd" 

config/i386/constraints.md has

(define_register_constraint "Yd"
 "TARGET_AVX512DQ ? ALL_SSE_REGS : TARGET_SSE4_1 ? SSE_REGS : NO_REGS"
 "@internal Any EVEX encodable SSE register (@code{%xmm0-%xmm31}) for AVX512DQ target or any SSE register for SSE4_1 target.")

Comments for "Yd" should mention AVX512DQ, not AVX512BW.

	* config/i386/constraints.md (Yd): Replace AVX512BW with AVX512DQ
	in comments

From-SVN: r268759
parent 05eca511
Showing with 6 additions and 1 deletions
gcc/ChangeLog
2019-02-10 H.J. Lu <hongjiu.lu@intel.com>
* config/i386/constraints.md (Yd): Replace AVX512BW with AVX512DQ
in comments
2019-02-10 Chung-Ju Wu <jasonwucj@gmail.com> 2019-02-10 Chung-Ju Wu <jasonwucj@gmail.com>
* config.gcc (with_nds32_lib): Set default --with-nds32-lib correctly. * config.gcc (with_nds32_lib): Set default --with-nds32-lib correctly.
......
gcc/config/i386/constraints.md
...@@ -96,7 +96,7 @@ ...@@ -96,7 +96,7 @@
;; We use the Y prefix to denote any number of conditional register sets: ;; We use the Y prefix to denote any number of conditional register sets:
;; z First SSE register. ;; z First SSE register.
;; d any EVEX encodable SSE register for AVX512BW target or ;; d any EVEX encodable SSE register for AVX512DQ target or
;; any SSE register for SSE4_1 target. ;; any SSE register for SSE4_1 target.
;; p Integer register when TARGET_PARTIAL_REG_STALL is disabled ;; p Integer register when TARGET_PARTIAL_REG_STALL is disabled
;; a Integer register when zero extensions with AND are disabled ;; a Integer register when zero extensions with AND are disabled
......
Markdown is supported
0% or
You are about to add 0 people to the discussion. Proceed with caution.
Finish editing this message first!
Please register or to comment