Skip to content
Projects
Groups
Snippets
Help
This project
Loading...
Sign in / Register
Toggle navigation
R
riscv-gcc-1
Overview
Overview
Details
Activity
Cycle Analytics
Repository
Repository
Files
Commits
Branches
Tags
Contributors
Graph
Compare
Charts
Issues
0
Issues
0
List
Board
Labels
Milestones
Merge Requests
0
Merge Requests
0
CI / CD
CI / CD
Pipelines
Jobs
Schedules
Charts
Wiki
Wiki
Snippets
Snippets
Members
Members
Collapse sidebar
Close sidebar
Activity
Graph
Charts
Create a new issue
Jobs
Commits
Issue Boards
Open sidebar
lvzhengyang
riscv-gcc-1
Commits
8d36d33b
Commit
8d36d33b
authored
Nov 17, 1994
by
Richard Kenner
Browse files
Options
Browse Files
Download
Email Patches
Plain Diff
(some_operand): New function.
From-SVN: r8481
parent
02df8aba
Hide whitespace changes
Inline
Side-by-side
Showing
1 changed file
with
24 additions
and
0 deletions
+24
-0
gcc/config/alpha/alpha.c
+24
-0
No files found.
gcc/config/alpha/alpha.c
View file @
8d36d33b
...
...
@@ -280,6 +280,30 @@ reg_or_cint_operand (op, mode)
return
GET_CODE
(
op
)
==
CONST_INT
||
register_operand
(
op
,
mode
);
}
/* Return 1 if OP is something that can be reloaded into a register;
if it is a MEM, it need not be valid. */
int
some_operand
(
op
,
mode
)
register
rtx
op
;
enum
machine_mode
mode
;
{
if
(
mode
!=
VOIDmode
&&
GET_MODE
(
op
)
!=
VOIDmode
&&
mode
!=
GET_MODE
(
op
))
return
0
;
switch
(
GET_CODE
(
op
))
{
case
REG
:
case
MEM
:
case
CONST_DOUBLE
:
case
CONST_INT
:
case
LABEL_REF
:
case
SYMBOL_REF
:
case
CONST
:
return
1
;
case
SUBREG
:
return
some_operand
(
SUBREG_REG
(
op
),
VOIDmode
);
}
return
0
;
}
/* Return 1 if OP is a valid operand for the source of a move insn. */
int
...
...
Write
Preview
Markdown
is supported
0%
Try again
or
attach a new file
Attach a file
Cancel
You are about to add
0
people
to the discussion. Proceed with caution.
Finish editing this message first!
Cancel
Please
register
or
sign in
to comment