Commit 8cc59ac5 by Kito Cheng

PR target/93995 ICE in patch_jump_insn, at cfgrtl.c:1290 on riscv64-linux-gnu

Last code gen change of LTGT didn't consider the situation of cbranch with LTGT,
branch only support few compare codes.

gcc/ChangeLog

	* config/riscv/riscv.c (riscv_emit_float_compare): Using NE to compare
	the result of IOR.

gcc/testsuite/ChangeLog

	* gcc.dg/pr93995.c: New.
parent 6b3302da
2020-03-04 Kito Cheng <kito.cheng@sifive.com>
PR target/93995
* config/riscv/riscv.c (riscv_emit_float_compare): Using NE to compare
the result of IOR.
2020-03-03 Dennis Zhang <dennis.zhang@arm.com> 2020-03-03 Dennis Zhang <dennis.zhang@arm.com>
* config/arm/arm_bf16.h (vcvtah_f32_bf16, vcvth_bf16_f32): New. * config/arm/arm_bf16.h (vcvtah_f32_bf16, vcvth_bf16_f32): New.
......
...@@ -2299,9 +2299,10 @@ riscv_emit_float_compare (enum rtx_code *code, rtx *op0, rtx *op1) ...@@ -2299,9 +2299,10 @@ riscv_emit_float_compare (enum rtx_code *code, rtx *op0, rtx *op1)
case LTGT: case LTGT:
/* (a < b) | (a > b) */ /* (a < b) | (a > b) */
*code = IOR; tmp0 = riscv_force_binary (word_mode, LT, cmp_op0, cmp_op1);
*op0 = riscv_force_binary (word_mode, LT, cmp_op0, cmp_op1); tmp1 = riscv_force_binary (word_mode, GT, cmp_op0, cmp_op1);
*op1 = riscv_force_binary (word_mode, GT, cmp_op0, cmp_op1); *op0 = riscv_force_binary (word_mode, IOR, tmp0, tmp1);
*op1 = const0_rtx;
break; break;
default: default:
......
2020-03-04 Kito Cheng <kito.cheng@sifive.com>
PR target/93995
* gcc.dg/pr93995.c: New.
2020-03-03 Marek Polacek <polacek@redhat.com> 2020-03-03 Marek Polacek <polacek@redhat.com>
PR c++/90505 - mismatch in template argument deduction. PR c++/90505 - mismatch in template argument deduction.
......
/* PR target/93995 */
/* { dg-do run } */
/* { dg-options "-O2 -fno-trapping-math" } */
double s1[4], s2[4], s3[64];
int
main (void)
{
int i;
asm volatile ("" : : : "memory");
for (i = 0; i < 4; i++)
s3[0 * 4 + i] = __builtin_isgreater (s1[i], s2[i]) ? -1.0 : 0.0;
for (i = 0; i < 4; i++)
s3[1 * 4 + i] = (!__builtin_isgreater (s1[i], s2[i])) ? -1.0 : 0.0;
for (i = 0; i < 4; i++)
s3[2 * 4 + i] = __builtin_isgreaterequal (s1[i], s2[i]) ? -1.0 : 0.0;
for (i = 0; i < 4; i++)
s3[3 * 4 + i] = (!__builtin_isgreaterequal (s1[i], s2[i])) ? -1.0 : 0.0;
for (i = 0; i < 4; i++)
s3[4 * 4 + i] = __builtin_isless (s1[i], s2[i]) ? -1.0 : 0.0;
for (i = 0; i < 4; i++)
s3[5 * 4 + i] = (!__builtin_isless (s1[i], s2[i])) ? -1.0 : 0.0;
for (i = 0; i < 4; i++)
s3[6 * 4 + i] = __builtin_islessequal (s1[i], s2[i]) ? -1.0 : 0.0;
for (i = 0; i < 4; i++)
s3[7 * 4 + i] = (!__builtin_islessequal (s1[i], s2[i])) ? -1.0 : 0.0;
for (i = 0; i < 4; i++)
s3[8 * 4 + i] = __builtin_islessgreater (s1[i], s2[i]) ? -1.0 : 0.0;
for (i = 0; i < 4; i++)
s3[9 * 4 + i] = (!__builtin_islessgreater (s1[i], s2[i])) ? -1.0 : 0.0;
for (i = 0; i < 4; i++)
s3[10 * 4 + i] = __builtin_isunordered (s1[i], s2[i]) ? -1.0 : 0.0;
for (i = 0; i < 4; i++)
s3[11 * 4 + i] = (!__builtin_isunordered (s1[i], s2[i])) ? -1.0 : 0.0;
for (i = 0; i < 4; i++)
s3[12 * 4 + i] = s1[i] > s2[i] ? -1.0 : 0.0;
for (i = 0; i < 4; i++)
s3[13 * 4 + i] = s1[i] >= s2[i] ? -1.0 : 0.0;
for (i = 0; i < 4; i++)
s3[14 * 4 + i] = s1[i] < s2[i] ? -1.0 : 0.0;
for (i = 0; i < 4; i++)
s3[15 * 4 + i] = s1[i] <= s2[i] ? -1.0 : 0.0;
asm volatile ("" : : : "memory");
return 0;
}
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