[NDS32] Add abssi2 pattern.

gcc/
	* common/config/nds32/nds32-common.c (TARGET_DEFAULT_TARGET_FLAGS): Add
	MASK_HW_ABS.
	* config/nds32/nds32.md (abssi2): New pattern.

From-SVN: r260398

gcc/ChangeLog

+2018-05-19  Chung-Ju Wu  <jasonwucj@gmail.com>
+
+	* common/config/nds32/nds32-common.c (TARGET_DEFAULT_TARGET_FLAGS): Add
+	MASK_HW_ABS.
+	* config/nds32/nds32.md (abssi2): New pattern.
+
 2018-05-19  Uros Bizjak  <ubizjak@gmail.com>
 
 	* config/i386/i386.md (rex64namesuffix): New mode attribute.

gcc/common/config/nds32/nds32-common.c

@@ -103,6 +103,7 @@ static const struct default_options nds32_option_optimization_table[] =
      TARGET_EXT_PERF   : Generate performance extention instrcution.
      TARGET_EXT_PERF2  : Generate performance extention version 2 instrcution.
      TARGET_EXT_STRING : Generate string extention instrcution.
+     TARGET_HW_ABS     : Generate hardware abs instruction.
      TARGET_CMOV       : Generate conditional move instruction.  */
 #undef TARGET_DEFAULT_TARGET_FLAGS
 #define TARGET_DEFAULT_TARGET_FLAGS		\
@@ -113,6 +114,7 @@ static const struct default_options nds32_option_optimization_table[] =
    | MASK_EXT_PERF				\
    | MASK_EXT_PERF2				\
    | MASK_EXT_STRING				\
+   | MASK_HW_ABS				\
    | MASK_CMOV)
 
 #undef TARGET_HANDLE_OPTION

gcc/config/nds32/nds32.md

@@ -2086,6 +2086,20 @@
 
 ;; Performance Extension
 
+; If -fwrapv option is issued, GCC expects there will be
+; signed overflow situation.  So the ABS(INT_MIN) is still INT_MIN
+; (e.g. ABS(0x80000000)=0x80000000).
+; However, the hardware ABS instruction of nds32 target
+; always performs saturation: abs 0x80000000 -> 0x7fffffff.
+; So that we can only enable abssi2 pattern if flag_wrapv is NOT presented.
+(define_insn "abssi2"
+  [(set (match_operand:SI 0 "register_operand"         "=r")
+	(abs:SI (match_operand:SI 1 "register_operand" " r")))]
+  "TARGET_EXT_PERF && TARGET_HW_ABS && !flag_wrapv"
+  "abs\t%0, %1"
+  [(set_attr "type" "alu")
+   (set_attr "length" "4")])
+
 (define_insn "clzsi2"
   [(set (match_operand:SI 0 "register_operand"         "=r")
 	(clz:SI (match_operand:SI 1 "register_operand" " r")))]