Commit 8c5fd59f by Uros Bizjak Committed by Uros Bizjak

invoke.texi (i386 and x86-64 Options): Clarify -msahf option.

       * doc/invoke.texi (i386 and x86-64 Options): Clarify -msahf option.

From-SVN: r122910
parent e31657e8
2007-03-14 Uros Bizjak <ubizjak@gmail.com>
* doc/invoke.texi (i386 and x86-64 Options): Clarify -msahf option.
2007-03-13 Seongbae Park <seongbae.park@gmail.com> 2007-03-13 Seongbae Park <seongbae.park@gmail.com>
PR tree-optimization/30590 PR tree-optimization/30590
......
...@@ -10091,11 +10091,12 @@ atomic built-in functions: see @ref{Atomic Builtins} for details. ...@@ -10091,11 +10091,12 @@ atomic built-in functions: see @ref{Atomic Builtins} for details.
@item -msahf @item -msahf
@opindex -msahf @opindex -msahf
This option will enable GCC to use SAHF instruction in generated code. Early This option will enable GCC to use SAHF instruction in generated 64-bit code.
Intel CPUs with Intel 64 lacked LAHF and SAHF instructions supported by AMD64 Early Intel CPUs with Intel 64 lacked LAHF and SAHF instructions supported
until introduction of Pentium 4 G1 step in December 2005. LAHF and SAHF are by AMD64 until introduction of Pentium 4 G1 step in December 2005. LAHF and
load and store instructions, respectively, for certain status flags. These SAHF are load and store instructions, respectively, for certain status flags.
instructions are used for virtualization and floating-point condition handling. In 64-bit mode, SAHF instruction is used to optimize @code{fmod}, @code{drem}
or @code{remainder} built-in functions: see @ref{Other Builtins} for details.
@item -mpush-args @item -mpush-args
@itemx -mno-push-args @itemx -mno-push-args
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