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lvzhengyang
riscv-gcc-1
Commits
8bffcaf6
Commit
8bffcaf6
authored
Feb 25, 1994
by
Richard Kenner
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(mul*): Disallow multiply by constant.
From-SVN: r6621
parent
bcb58dfc
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gcc/config/alpha/alpha.md
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gcc/config/alpha/alpha.md
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8bffcaf6
...
@@ -328,25 +328,25 @@
...
@@ -328,25 +328,25 @@
(define_insn "mulsi3"
(define_insn "mulsi3"
[
(set (match_operand:SI 0 "register_operand" "=r")
[
(set (match_operand:SI 0 "register_operand" "=r")
(mult:SI (match_operand:SI 1 "reg_or_0_operand" "%rJ")
(mult:SI (match_operand:SI 1 "reg_or_0_operand" "%rJ")
(match_operand:SI 2 "reg_or_
8bit_operand" "rI
")))]
(match_operand:SI 2 "reg_or_
0_operand" "rJ
")))]
""
""
"mull %r1,%2,%0"
"mull %r1,%
r
2,%0"
[
(set_attr "type" "imull")
]
)
[
(set_attr "type" "imull")
]
)
(define_insn ""
(define_insn ""
[
(set (match_operand:DI 0 "register_operand" "=r")
[
(set (match_operand:DI 0 "register_operand" "=r")
(sign_extend:DI (mult:SI (match_operand:SI 1 "reg_or_0_operand" "%rJ")
(sign_extend:DI (mult:SI (match_operand:SI 1 "reg_or_0_operand" "%rJ")
(match_operand:SI 2 "reg_or_
8bit_operand" "rI
"))))]
(match_operand:SI 2 "reg_or_
0_operand" "rJ
"))))]
""
""
"mull %r1,%2,%0"
"mull %r1,%
r
2,%0"
[
(set_attr "type" "imull")
]
)
[
(set_attr "type" "imull")
]
)
(define_insn "muldi3"
(define_insn "muldi3"
[
(set (match_operand:DI 0 "register_operand" "=r")
[
(set (match_operand:DI 0 "register_operand" "=r")
(mult:DI (match_operand:DI 1 "reg_or_0_operand" "%rJ")
(mult:DI (match_operand:DI 1 "reg_or_0_operand" "%rJ")
(match_operand:DI 2 "reg_or_
8bit_operand" "rI
")))]
(match_operand:DI 2 "reg_or_
0_operand" "rJ
")))]
""
""
"mulq %r1,%2,%0"
"mulq %r1,%
r
2,%0"
[
(set_attr "type" "imulq")
]
)
[
(set_attr "type" "imulq")
]
)
;; The divide and remainder operations always take their inputs from
;; The divide and remainder operations always take their inputs from
...
...
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