Commit 8bd5e1f7 by Eric Botcazou Committed by Eric Botcazou

re PR target/81988 (invalid std instruction with odd register)

	PR target/81988
	* config/sparc/sparc.md (mulsi3): Rename into *mulsi3_sp32.
	(*mulsi3_sp64): New instruction.
	(mulsi3): New expander.

From-SVN: r251904
parent edcc77db
2017-09-07 Eric Botcazou <ebotcazou@adacore.com>
PR target/81988
* config/sparc/sparc.md (mulsi3): Rename into *mulsi3_sp32.
(*mulsi3_sp64): New instruction.
(mulsi3): New expander.
2017-09-08 Uros Bizjak <ubizjak@gmail.com> 2017-09-08 Uros Bizjak <ubizjak@gmail.com>
* config/alpha/alpha.c (alpha_print_operand) <case 'S'>: Remove. * config/alpha/alpha.c (alpha_print_operand) <case 'S'>: Remove.
......
...@@ -4517,7 +4517,14 @@ visl") ...@@ -4517,7 +4517,14 @@ visl")
;; The 32-bit multiply/divide instructions are deprecated on v9, but at ;; The 32-bit multiply/divide instructions are deprecated on v9, but at
;; least in UltraSPARC I, II and IIi it is a win tick-wise. ;; least in UltraSPARC I, II and IIi it is a win tick-wise.
(define_insn "mulsi3" (define_expand "mulsi3"
[(set (match_operand:SI 0 "register_operand" "")
(mult:SI (match_operand:SI 1 "arith_operand" "")
(match_operand:SI 2 "arith_operand" "")))]
"TARGET_HARD_MUL || TARGET_ARCH64"
"")
(define_insn "*mulsi3_sp32"
[(set (match_operand:SI 0 "register_operand" "=r") [(set (match_operand:SI 0 "register_operand" "=r")
(mult:SI (match_operand:SI 1 "arith_operand" "%r") (mult:SI (match_operand:SI 1 "arith_operand" "%r")
(match_operand:SI 2 "arith_operand" "rI")))] (match_operand:SI 2 "arith_operand" "rI")))]
...@@ -4525,6 +4532,14 @@ visl") ...@@ -4525,6 +4532,14 @@ visl")
"smul\t%1, %2, %0" "smul\t%1, %2, %0"
[(set_attr "type" "imul")]) [(set_attr "type" "imul")])
(define_insn "*mulsi3_sp64"
[(set (match_operand:SI 0 "register_operand" "=r")
(mult:SI (match_operand:SI 1 "arith_operand" "%r")
(match_operand:SI 2 "arith_operand" "rI")))]
"TARGET_ARCH64"
"mulx\t%1, %2, %0"
[(set_attr "type" "imul")])
(define_expand "muldi3" (define_expand "muldi3"
[(set (match_operand:DI 0 "register_operand" "") [(set (match_operand:DI 0 "register_operand" "")
(mult:DI (match_operand:DI 1 "arith_operand" "") (mult:DI (match_operand:DI 1 "arith_operand" "")
......
2017-09-07 Eric Botcazou <ebotcazou@adacore.com> 2017-09-07 Eric Botcazou <ebotcazou@adacore.com>
* gcc.dg/pr81988.c: New test.
2017-09-07 Eric Botcazou <ebotcazou@adacore.com>
* gnat.dg/opt67.adb: New test. * gnat.dg/opt67.adb: New test.
* gnat.dg/opt67_pkg.ad[sb]: New helper. * gnat.dg/opt67_pkg.ad[sb]: New helper.
......
/* PR target/81988 */
/* Testcase by James Cowgill <jcowgill+gcc@jcowgill.uk> */
/* { dg-do assemble } */
/* { dg-require-effective-target pie } */
/* { dg-options "-O3 -fpie" } */
int c, d;
short **e;
int *a;
void foo(void)
{
int g[64 * 35], *h = g;
do {
short *f = e[d];
for (int i = 0; i < 4; i++)
a[i] = a[i] + (h[364] + f[4] * h[64] + f[5] * h[i] + f[6] * h[i + 3 * 4] +
f[7] * h[i + 4]);
} while (c);
}
Markdown is supported
0% or
You are about to add 0 people to the discussion. Proceed with caution.
Finish editing this message first!
Please register or to comment