re PR target/54236 ([SH] Improve addc and subc insn utilization)

	PR target/54236
	* config/sh/sh.md (*addc): Add pattern to handle one bit left shifts.

	PR target/54236
	* gcc.target/sh/pr54236-1.c (test_08): Add one bit left shift case.

From-SVN: r191489

gcc/ChangeLog

 2012-09-19  Oleg Endo  <olegendo@gcc.gnu.org>
 
+	PR target/54236
+	* config/sh/sh.md (*addc): Add pattern to handle one bit left shifts.
+
+2012-09-19  Oleg Endo  <olegendo@gcc.gnu.org>
+
 	* config/sh/sh.md (prologue, epilogue): Use braced strings.
 
 2012-09-19  Eric Botcazou  <ebotcazou@adacore.com>

gcc/config/sh/sh.md

@@ -1787,6 +1787,22 @@
 				          (reg:SI T_REG)))
 	      (clobber (reg:SI T_REG))])])
 
+;; Left shifts by one are usually done with an add insn to avoid T_REG
+;; clobbers.  Thus addc can also be used to do something like '(x << 1) + 1'.
+(define_insn_and_split "*addc"
+  [(set (match_operand:SI 0 "arith_reg_dest")
+	(plus:SI (mult:SI (match_operand:SI 1 "arith_reg_operand")
+			  (const_int 2))
+		 (const_int 1)))
+   (clobber (reg:SI T_REG))]
+  "TARGET_SH1"
+  "#"
+  "&& 1"
+  [(set (reg:SI T_REG) (const_int 1))
+   (parallel [(set (match_dup 0) (plus:SI (plus:SI (match_dup 1) (match_dup 1))
+				          (reg:SI T_REG)))
+	      (clobber (reg:SI T_REG))])])
+
 ;; Sometimes combine will try to do 'reg + (0-reg) + 1' if the *addc pattern
 ;; matched.  Split this up into a simple sub add sequence, as this will save
 ;; us one sett insn.

gcc/testsuite/ChangeLog

+2012-09-19  Oleg Endo  <olegendo@gcc.gnu.org>
+
+	PR target/54236
+	* gcc.target/sh/pr54236-1.c (test_08): Add one bit left shift case.
+
 2012-09-19  Eric Botcazou  <ebotcazou@adacore.com>
 
 	* gcc.c-torture/execute/20120919-1.c: New test.

gcc/testsuite/gcc.target/sh/pr54236-1.c

@@ -4,9 +4,9 @@
 /* { dg-do compile { target "sh*-*-*" } } */
 /* { dg-options "-O1" } */
 /* { dg-skip-if "" { "sh*-*-*" } { "-m5*"} { "" } } */
-/* { dg-final { scan-assembler-times "addc" 3 } } */
+/* { dg-final { scan-assembler-times "addc" 4 } } */
 /* { dg-final { scan-assembler-times "subc" 3 } } */
-/* { dg-final { scan-assembler-times "sett" 4 } } */
+/* { dg-final { scan-assembler-times "sett" 5 } } */
 /* { dg-final { scan-assembler-times "negc" 1 } } */
 /* { dg-final { scan-assembler-not "movt" } } */
 
@@ -74,3 +74,10 @@ test_07 (int *vec)
 
   return vi;
 }
+
+int
+test_08 (int a)
+{
+  /* 1x addc, 1x sett  */
+  return (a << 1) + 1;
+}