mn10300.md (addsi): `inc4' on address registers does not modify cc...

* config/mn10300/mn10300.md (addsi): `inc4' on address
registers does not modify cc, but `inc' on an extended
register does.

From-SVN: r33363

gcc/ChangeLog

+Sun Apr 23 20:16:49 2000  Alexandre Oliva  <aoliva@cygnus.com>
+
+	* config/mn10300/mn10300.md (addsi): `inc4' on address
+	registers does not modify cc, but `inc' on an extended
+	register does.
+
 Sun Apr 23 16:24:35 2000  Denis Chertykov  <denisc@overta.ru>
 
 	* reload.c (find_equiv_reg): Checks all valueno regs

gcc/config/mn10300/mn10300.md

@@ -760,9 +760,9 @@
 }")
 
 (define_insn ""
-  [(set (match_operand:SI 0 "register_operand" "=dx,ax,ax,dax,xy,!dax")
-	(plus:SI (match_operand:SI 1 "register_operand" "%0,0,0,0,0,dax")
-		 (match_operand:SI 2 "nonmemory_operand" "J,J,L,daxi,i,dax")))]
+  [(set (match_operand:SI 0 "register_operand" "=dx,a,x,a,dax,xy,!dax")
+	(plus:SI (match_operand:SI 1 "register_operand" "%0,0,0,0,0,0,dax")
+		 (match_operand:SI 2 "nonmemory_operand" "J,J,L,L,daxi,i,dax")))]
   "TARGET_AM33"
   "*
 {
@@ -772,11 +772,12 @@
     case 1:
       return \"inc %0\";
     case 2:
-      return \"inc4 %0\";
     case 3:
+      return \"inc4 %0\";
     case 4:
-      return \"add %2,%0\";
     case 5:
+      return \"add %2,%0\";
+    case 6:
       {
 	enum reg_class src1_class, src2_class, dst_class;
 
@@ -835,10 +836,10 @@
       abort ();
     }
 }"
-  [(set_attr "cc" "set_zn,none_0hit,none_0hit,set_zn,none_0hit,set_zn")])
+  [(set_attr "cc" "set_zn,none_0hit,set_zn,none_0hit,set_zn,none_0hit,set_zn")])
 
 (define_insn ""
-  [(set (match_operand:SI 0 "register_operand" "=dx,ax,ax,dax,xy,!dax")
+  [(set (match_operand:SI 0 "register_operand" "=dx,a,a,dax,xy,!dax")
 	(plus:SI (match_operand:SI 1 "register_operand" "%0,0,0,0,0,dax")
 		 (match_operand:SI 2 "nonmemory_operand" "J,J,L,daxi,i,dax")))]
   ""